#include "InstructionSet.hpp"

#include "Operand.hpp"

#include <string.h>
#include <stdio.h>
#include <assert.h>

namespace SoftWire
{
	const Instruction::Syntax InstructionSet::instructionSet[] =
	{
		/*
			Encoding syntax:
			----------------
			+r Add register value to opcode
			/# Value for Mod R/M register field encoding
			/r Effective address encoding
			ib Byte immediate
			iw Word immediate
			id Dword immediate
			-b Byte relative address
			-i Word or dword relative address
			p0 LOCK instruction prefix (F0h)
			p2 REPNE/REPNZ instruction prefix (F2h)
			p3 REP/REPE/REPZ instruction prefix (F3h) (also SSE prefix)
			po Offset override prefix (66h)
			pa Address override prefix (67h)

			Read Keywords.cpp for operands syntax
		*/

		// x86 instruction set
		{"AAA",				"",							"37",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"AAD",				"",							"D5 0A",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"AAD",				"imm",						"D5 ib",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"AAM",				"",							"D4 0A",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"AAM",				"imm",						"D4 ib",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"AAS",				"",							"3F",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"ADC",				"r/m8,reg8",				"10 /r",				Instruction::CPU_8086},
		{"ADC",				"r/m16,reg16",				"po 11 /r",				Instruction::CPU_8086},
		{"ADC",				"r/m32,reg32",				"po 11 /r",				Instruction::CPU_386},
		{"ADC",				"r/m64,reg64",				"po 11 /r",				Instruction::CPU_X64},
		{"ADC",				"reg8,r/m8",				"12 /r",				Instruction::CPU_8086},
		{"ADC",				"reg16,r/m16",				"po 13 /r",				Instruction::CPU_8086},
		{"ADC",				"reg32,r/m32",				"po 13 /r",				Instruction::CPU_386},
		{"ADC",				"reg64,r/m64",				"po 13 /r",				Instruction::CPU_X64},
		{"ADC",				"BYTE r/m8,imm8",			"80 /2 ib",				Instruction::CPU_8086},
		{"ADC",				"WORD r/m16,imm16",			"po 81 /2 iw",			Instruction::CPU_8086},
		{"ADC",				"DWORD r/m32,imm32",		"po 81 /2 id",			Instruction::CPU_386},
		{"ADC",				"QWORD r/m64,imm32",		"po 81 /2 id",			Instruction::CPU_X64},
		{"ADC",				"WORD r/m16,imm8",			"po 83 /2 ib",			Instruction::CPU_8086},
		{"ADC",				"DWORD r/m32,imm8",			"po 83 /2 ib",			Instruction::CPU_386},
		{"ADC",				"QWORD r/m64,imm8",			"po 83 /2 ib",			Instruction::CPU_X64},
		{"ADC",				"AL,imm8",					"14 ib",				Instruction::CPU_8086},
		{"ADC",				"AX,imm16",					"po 15 iw",				Instruction::CPU_8086},
		{"ADC",				"EAX,imm32",				"po 15 id",				Instruction::CPU_386},
		{"ADC",				"RAX,imm32",				"po 15 id",				Instruction::CPU_X64},
		{"ADD",				"r/m8,reg8",				"00 /r",				Instruction::CPU_8086},
		{"ADD",				"r/m16,reg16",				"po 01 /r",				Instruction::CPU_8086},
		{"ADD",				"r/m32,reg32",				"po 01 /r",				Instruction::CPU_386},
		{"ADD",				"r/m64,reg64",				"po 01 /r",				Instruction::CPU_X64},
		{"ADD",				"reg8,r/m8",				"02 /r",				Instruction::CPU_8086},
		{"ADD",				"reg16,r/m16",				"po 03 /r",				Instruction::CPU_8086},
		{"ADD",				"reg32,r/m32",				"po 03 /r",				Instruction::CPU_386},
		{"ADD",				"reg64,r/m64",				"po 03 /r",				Instruction::CPU_X64},
		{"ADD",				"BYTE r/m8,imm8",			"80 /0 ib",				Instruction::CPU_8086},
		{"ADD",				"WORD r/m16,imm16",			"po 81 /0 iw",			Instruction::CPU_8086},
		{"ADD",				"DWORD r/m32,imm32",		"po 81 /0 id",			Instruction::CPU_386},
		{"ADD",				"QWORD r/m64,imm32",		"po 81 /0 id",			Instruction::CPU_X64},
		{"ADD",				"WORD r/m16,imm8",			"po 83 /0 ib",			Instruction::CPU_8086},
		{"ADD",				"DWORD r/m32,imm8",			"po 83 /0 ib",			Instruction::CPU_386},
		{"ADD",				"QWORD r/m64,imm8",			"po 83 /0 ib",			Instruction::CPU_X64},
		{"ADD",				"AL,imm8",					"04 ib",				Instruction::CPU_8086},
		{"ADD",				"AX,imm16",					"po 05 iw",				Instruction::CPU_8086},
		{"ADD",				"EAX,imm32",				"po 05 id",				Instruction::CPU_386},
		{"ADD",				"RAX,imm32",				"po 05 id",				Instruction::CPU_X64},
		{"ADDPD",			"xmmreg,r/m128",			"66 0F 58 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"ADDPS",			"xmmreg,r/m128",			"0F 58 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"ADDSD",			"xmmreg,xmm64",				"p2 0F 58 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"ADDSS",			"xmmreg,xmm32",				"p3 0F 58 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"ADDSUBPD",		"xmmreg,r/m128",			"66 0F D0 /r",			Instruction::CPU_PNI},
		{"ADDSUBPS",		"xmmreg,r/m128",			"p2 0F D0 /r",			Instruction::CPU_PNI},
		{"ALIGN",			"imm",						"p1 90"},				// Special 'instruction', indicated by the 'p1' prefix
		{"AND",				"r/m8,reg8",				"20 /r",				Instruction::CPU_8086},
		{"AND",				"r/m16,reg16",				"po 21 /r",				Instruction::CPU_8086},
		{"AND",				"r/m32,reg32",				"po 21 /r",				Instruction::CPU_386},
		{"AND",				"r/m64,reg64",				"po 21 /r",				Instruction::CPU_X64},
		{"AND",				"reg8,r/m8",				"22 /r",				Instruction::CPU_8086},
		{"AND",				"reg16,r/m16",				"po 23 /r",				Instruction::CPU_8086},
		{"AND",				"reg32,r/m32",				"po 23 /r",				Instruction::CPU_386},
		{"AND",				"reg64,r/m64",				"po 23 /r",				Instruction::CPU_X64},
		{"AND",				"BYTE r/m8,imm8",			"80 /4 ib",				Instruction::CPU_8086},
		{"AND",				"WORD r/m16,imm16",			"po 81 /4 iw",			Instruction::CPU_8086},
		{"AND",				"DWORD r/m32,imm32",		"po 81 /4 id",			Instruction::CPU_386},
		{"AND",				"QWORD r/m64,imm32",		"po 81 /4 id",			Instruction::CPU_X64},
		{"AND",				"WORD r/m16,imm8",			"po 83 /4 ib",			Instruction::CPU_8086},
		{"AND",				"DWORD r/m32,imm8",			"po 83 /4 ib",			Instruction::CPU_386},
		{"AND",				"QWORD r/m64,imm8",			"po 83 /4 ib",			Instruction::CPU_X64},
		{"AND",				"AL,imm8",					"24 ib",				Instruction::CPU_8086},
		{"AND",				"AX,imm16",					"po 25 iw",				Instruction::CPU_8086},
		{"AND",				"EAX,imm32",				"po 25 id",				Instruction::CPU_386},
		{"AND",				"RAX,imm32",				"po 25 id",				Instruction::CPU_X64},
		{"ANDNPD",			"xmmreg,r/m128",			"66 0F 55 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"ANDNPS",			"xmmreg,r/m128",			"0F 55 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"ANDPD",			"xmmreg,r/m128",			"66 0F 54 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"ANDPS",			"xmmreg,r/m128",			"0F 54 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
	//	{"ARPL",			"r/m16,reg16",				"63 /r",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"BLENDPD",			"xmmreg,r/m128,imm8",		"66 0F 3A 0D /r ib",	Instruction::CPU_SSE4_1},
		{"BLENDPS",			"xmmreg,r/m128,imm8",		"66 0F 3A 0C /r ib",	Instruction::CPU_SSE4_1},
		{"BLENDVPS",		"xmmreg,r/m128",			"66 0F 38 14 /r",		Instruction::CPU_SSE4_1},
		{"BOUND",			"reg16,mem",				"po 62 /r",				Instruction::CPU_186 | Instruction::CPU_INVALID64},
		{"BOUND",			"reg32,mem",				"po 62 /r",				Instruction::CPU_386 | Instruction::CPU_INVALID64},
		{"BSF",				"reg16,r/m16",				"po 0F BC /r",			Instruction::CPU_386},
		{"BSF",				"reg32,r/m32",				"po 0F BC /r",			Instruction::CPU_386},
		{"BSF",				"reg64,r/m64",				"po 0F BC /r",			Instruction::CPU_X64},
		{"BSR",				"reg16,r/m16",				"po 0F BD /r",			Instruction::CPU_386},
		{"BSR",				"reg32,r/m32",				"po 0F BD /r",			Instruction::CPU_386},
		{"BSR",				"reg64,r/m64",				"po 0F BD /r",			Instruction::CPU_X64},
		{"BSWAP",			"reg32",					"po 0F C8 +r",			Instruction::CPU_486},
		{"BSWAP",			"reg64",					"po 0F C8 +r",			Instruction::CPU_X64},
		{"BT",				"r/m16,reg16",				"po 0F A3 /r",			Instruction::CPU_386},
		{"BT",				"r/m32,reg32",				"po 0F A3 /r",			Instruction::CPU_386},
		{"BT",				"r/m64,reg64",				"po 0F A3 /r",			Instruction::CPU_X64},
		{"BT",				"WORD r/m16,imm8",			"po 0F BA /4 ib",		Instruction::CPU_386},
		{"BT",				"DWORD r/m32,imm8",			"po 0F BA /4 ib",		Instruction::CPU_386},
		{"BT",				"QWORD r/m64,imm8",			"po 0F BA /4 ib",		Instruction::CPU_X64},
		{"BTC",				"r/m16,reg16",				"po 0F BB /r",			Instruction::CPU_386},
		{"BTC",				"r/m32,reg32",				"po 0F BB /r",			Instruction::CPU_386},
		{"BTC",				"r/m64,reg64",				"po 0F BB /r",			Instruction::CPU_X64},
		{"BTC",				"WORD r/m16,imm8",			"po 0F BA /7 ib",		Instruction::CPU_386},
		{"BTC",				"DWORD r/m32,imm8",			"po 0F BA /7 ib",		Instruction::CPU_386},
		{"BTC",				"QWORD r/m64,imm8",			"po 0F BA /7 ib",		Instruction::CPU_X64},
		{"BTR",				"r/m16,reg16",				"po 0F B3 /r",			Instruction::CPU_386},
		{"BTR",				"r/m32,reg32",				"po 0F B3 /r",			Instruction::CPU_386},
		{"BTR",				"r/m64,reg64",				"po 0F B3 /r",			Instruction::CPU_X64},
		{"BTR",				"WORD r/m16,imm8",			"po 0F BA /6 ib",		Instruction::CPU_386},
		{"BTR",				"DWORD r/m32,imm8",			"po 0F BA /6 ib",		Instruction::CPU_386},
		{"BTR",				"QWORD r/m64,imm8",			"po 0F BA /6 ib",		Instruction::CPU_X64},
		{"BTS",				"r/m16,reg16",				"po 0F AB /r",			Instruction::CPU_386},
		{"BTS",				"r/m32,reg32",				"po 0F AB /r",			Instruction::CPU_386},
		{"BTS",				"r/m64,reg64",				"po 0F AB /r",			Instruction::CPU_X64},
		{"BTS",				"WORD r/m16,imm8",			"po 0F BA /5 ib",		Instruction::CPU_386},
		{"BTS",				"DWORD r/m32,imm8",			"po 0F BA /5 ib",		Instruction::CPU_386},
		{"BTS",				"QWORD r/m64,imm8",			"po 0F BA /5 ib",		Instruction::CPU_X64},
		{"CALL",			"imm",						"E8 -i",				Instruction::CPU_8086},
	//	{"CALL",			"imm:imm16",				"po 9A iw iw",			Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"CALL",			"imm:imm32",				"po 9A id iw",			Instruction::CPU_386 | Instruction::CPU_INVALID64},
	//	{"CALL",			"FAR mem16",				"po FF /3",				Instruction::CPU_8086},
	//	{"CALL",			"FAR mem32",				"po FF /3",				Instruction::CPU_386},
		{"CALL",			"WORD r/m16",				"po FF /2",				Instruction::CPU_8086},
		{"CALL",			"DWORD r/m32",				"po FF /2",				Instruction::CPU_386},
		{"CALL",			"QWORD r/m64",				"po FF /2",				Instruction::CPU_X64},
		{"CBW",				"",							"po 98",				Instruction::CPU_8086},
		{"CDQ",				"",							"po 99",				Instruction::CPU_386},
		{"CDQE",			"",							"po 98",				Instruction::CPU_X64},
		{"CLC",				"",							"F8",					Instruction::CPU_8086},
		{"CLD",				"",							"FC",					Instruction::CPU_8086},
		{"CLFLUSH",			"mem",						"0F AE /7",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CLI",				"",							"FA",					Instruction::CPU_8086},
	//	{"CLTS",			"",							"0F 06",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"CMC",				"",							"F5",					Instruction::CPU_8086},
		{"CMOVA",			"reg16,r/m16",				"po 0F 47 /r",			Instruction::CPU_P6},
		{"CMOVA",			"reg32,r/m32",				"po 0F 47 /r",			Instruction::CPU_P6},
		{"CMOVA",			"reg64,r/m64",				"po 0F 47 /r",			Instruction::CPU_X64},
		{"CMOVAE",			"reg16,r/m16",				"po 0F 43 /r",			Instruction::CPU_P6},
		{"CMOVAE",			"reg32,r/m32",				"po 0F 43 /r",			Instruction::CPU_P6},
		{"CMOVAE",			"reg64,r/m64",				"po 0F 43 /r",			Instruction::CPU_X64},
		{"CMOVB",			"reg16,r/m16",				"po 0F 42 /r",			Instruction::CPU_P6},
		{"CMOVB",			"reg32,r/m32",				"po 0F 42 /r",			Instruction::CPU_P6},
		{"CMOVB",			"reg64,r/m64",				"po 0F 42 /r",			Instruction::CPU_X64},
		{"CMOVBE",			"reg16,r/m16",				"po 0F 46 /r",			Instruction::CPU_P6},
		{"CMOVBE",			"reg32,r/m32",				"po 0F 46 /r",			Instruction::CPU_P6},
		{"CMOVBE",			"reg64,r/m64",				"po 0F 46 /r",			Instruction::CPU_X64},
		{"CMOVC",			"reg16,r/m16",				"po 0F 42 /r",			Instruction::CPU_P6},
		{"CMOVC",			"reg32,r/m32",				"po 0F 42 /r",			Instruction::CPU_P6},
		{"CMOVC",			"reg64,r/m64",				"po 0F 42 /r",			Instruction::CPU_X64},
		{"CMOVE",			"reg16,r/m16",				"po 0F 44 /r",			Instruction::CPU_P6},
		{"CMOVE",			"reg32,r/m32",				"po 0F 44 /r",			Instruction::CPU_P6},
		{"CMOVE",			"reg64,r/m64",				"po 0F 44 /r",			Instruction::CPU_X64},
		{"CMOVG",			"reg16,r/m16",				"po 0F 4F /r",			Instruction::CPU_P6},
		{"CMOVG",			"reg32,r/m32",				"po 0F 4F /r",			Instruction::CPU_P6},
		{"CMOVG",			"reg64,r/m64",				"po 0F 4F /r",			Instruction::CPU_X64},
		{"CMOVGE",			"reg16,r/m16",				"po 0F 4D /r",			Instruction::CPU_P6},
		{"CMOVGE",			"reg32,r/m32",				"po 0F 4D /r",			Instruction::CPU_P6},
		{"CMOVGE",			"reg64,r/m64",				"po 0F 4D /r",			Instruction::CPU_X64},
		{"CMOVL",			"reg16,r/m16",				"po 0F 4C /r",			Instruction::CPU_P6},
		{"CMOVL",			"reg32,r/m32",				"po 0F 4C /r",			Instruction::CPU_P6},
		{"CMOVL",			"reg64,r/m64",				"po 0F 4C /r",			Instruction::CPU_X64},
		{"CMOVLE",			"reg16,r/m16",				"po 0F 4E /r",			Instruction::CPU_P6},
		{"CMOVLE",			"reg32,r/m32",				"po 0F 4E /r",			Instruction::CPU_P6},
		{"CMOVLE",			"reg64,r/m64",				"po 0F 4E /r",			Instruction::CPU_X64},
		{"CMOVNA",			"reg16,r/m16",				"po 0F 46 /r",			Instruction::CPU_P6},
		{"CMOVNA",			"reg32,r/m32",				"po 0F 46 /r",			Instruction::CPU_P6},
		{"CMOVNA",			"reg64,r/m64",				"po 0F 46 /r",			Instruction::CPU_X64},
		{"CMOVNB",			"reg16,r/m16",				"po 0F 43 /r",			Instruction::CPU_P6},
		{"CMOVNB",			"reg32,r/m32",				"po 0F 43 /r",			Instruction::CPU_P6},
		{"CMOVNB",			"reg64,r/m64",				"po 0F 43 /r",			Instruction::CPU_X64},
		{"CMOVNBE",			"reg16,r/m16",				"po 0F 47 /r",			Instruction::CPU_P6},
		{"CMOVNBE",			"reg32,r/m32",				"po 0F 47 /r",			Instruction::CPU_P6},
		{"CMOVNBE",			"reg64,r/m64",				"po 0F 47 /r",			Instruction::CPU_X64},
		{"CMOVNC",			"reg16,r/m16",				"po 0F 43 /r",			Instruction::CPU_P6},
		{"CMOVNC",			"reg32,r/m32",				"po 0F 43 /r",			Instruction::CPU_P6},
		{"CMOVNC",			"reg64,r/m64",				"po 0F 43 /r",			Instruction::CPU_X64},
		{"CMOVNE",			"reg16,r/m16",				"po 0F 45 /r",			Instruction::CPU_P6},
		{"CMOVNE",			"reg32,r/m32",				"po 0F 45 /r",			Instruction::CPU_P6},
		{"CMOVNE",			"reg64,r/m64",				"po 0F 45 /r",			Instruction::CPU_X64},
		{"CMOVNEA",			"reg16,r/m16",				"po 0F 42 /r",			Instruction::CPU_P6},
		{"CMOVNEA",			"reg32,r/m32",				"po 0F 42 /r",			Instruction::CPU_P6},
		{"CMOVNEA",			"reg64,r/m64",				"po 0F 42 /r",			Instruction::CPU_X64},
		{"CMOVNG",			"reg16,r/m16",				"po 0F 4E /r",			Instruction::CPU_P6},
		{"CMOVNG",			"reg32,r/m32",				"po 0F 4E /r",			Instruction::CPU_P6},
		{"CMOVNG",			"reg64,r/m64",				"po 0F 4E /r",			Instruction::CPU_X64},
		{"CMOVNGE",			"reg16,r/m16",				"po 0F 4C /r",			Instruction::CPU_P6},
		{"CMOVNGE",			"reg32,r/m32",				"po 0F 4C /r",			Instruction::CPU_P6},
		{"CMOVNGE",			"reg64,r/m64",				"po 0F 4C /r",			Instruction::CPU_X64},
		{"CMOVNL",			"reg16,r/m16",				"po 0F 4D /r",			Instruction::CPU_P6},
		{"CMOVNL",			"reg32,r/m32",				"po 0F 4D /r",			Instruction::CPU_P6},
		{"CMOVNL",			"reg64,r/m64",				"po 0F 4D /r",			Instruction::CPU_X64},
		{"CMOVNLE",			"reg16,r/m16",				"po 0F 4F /r",			Instruction::CPU_P6},
		{"CMOVNLE",			"reg32,r/m32",				"po 0F 4F /r",			Instruction::CPU_P6},
		{"CMOVNLE",			"reg64,r/m64",				"po 0F 4F /r",			Instruction::CPU_X64},
		{"CMOVNO",			"reg16,r/m16",				"po 0F 41 /r",			Instruction::CPU_P6},
		{"CMOVNO",			"reg32,r/m32",				"po 0F 41 /r",			Instruction::CPU_P6},
		{"CMOVNO",			"reg64,r/m64",				"po 0F 41 /r",			Instruction::CPU_X64},
		{"CMOVNP",			"reg16,r/m16",				"po 0F 4B /r",			Instruction::CPU_P6},
		{"CMOVNP",			"reg32,r/m32",				"po 0F 4B /r",			Instruction::CPU_P6},
		{"CMOVNP",			"reg64,r/m64",				"po 0F 4B /r",			Instruction::CPU_X64},
		{"CMOVNS",			"reg16,r/m16",				"po 0F 49 /r",			Instruction::CPU_P6},
		{"CMOVNS",			"reg32,r/m32",				"po 0F 49 /r",			Instruction::CPU_P6},
		{"CMOVNS",			"reg64,r/m64",				"po 0F 49 /r",			Instruction::CPU_X64},
		{"CMOVNZ",			"reg16,r/m16",				"po 0F 45 /r",			Instruction::CPU_P6},
		{"CMOVNZ",			"reg32,r/m32",				"po 0F 45 /r",			Instruction::CPU_P6},
		{"CMOVNZ",			"reg64,r/m64",				"po 0F 45 /r",			Instruction::CPU_X64},
		{"CMOVO",			"reg16,r/m16",				"po 0F 40 /r",			Instruction::CPU_P6},
		{"CMOVO",			"reg32,r/m32",				"po 0F 40 /r",			Instruction::CPU_P6},
		{"CMOVO",			"reg64,r/m64",				"po 0F 40 /r",			Instruction::CPU_X64},
		{"CMOVP",			"reg16,r/m16",				"po 0F 4A /r",			Instruction::CPU_P6},
		{"CMOVP",			"reg32,r/m32",				"po 0F 4A /r",			Instruction::CPU_P6},
		{"CMOVP",			"reg64,r/m64",				"po 0F 4A /r",			Instruction::CPU_X64},
		{"CMOVPE",			"reg16,r/m16",				"po 0F 4A /r",			Instruction::CPU_P6},
		{"CMOVPE",			"reg32,r/m32",				"po 0F 4A /r",			Instruction::CPU_P6},
		{"CMOVPE",			"reg64,r/m64",				"po 0F 4A /r",			Instruction::CPU_X64},
		{"CMOVPO",			"reg16,r/m16",				"po 0F 4B /r",			Instruction::CPU_P6},
		{"CMOVPO",			"reg32,r/m32",				"po 0F 4B /r",			Instruction::CPU_P6},
		{"CMOVPO",			"reg64,r/m64",				"po 0F 4B /r",			Instruction::CPU_X64},
		{"CMOVS",			"reg16,r/m16",				"po 0F 48 /r",			Instruction::CPU_P6},
		{"CMOVS",			"reg32,r/m32",				"po 0F 48 /r",			Instruction::CPU_P6},
		{"CMOVS",			"reg32,r/m64",				"po 0F 48 /r",			Instruction::CPU_X64},
		{"CMOVZ",			"reg16,r/m16",				"po 0F 44 /r",			Instruction::CPU_P6},
		{"CMOVZ",			"reg32,r/m32",				"po 0F 44 /r",			Instruction::CPU_P6},
		{"CMOVZ",			"reg64,r/m64",				"po 0F 44 /r",			Instruction::CPU_X64},
		{"CMP",				"r/m8,reg8",				"38 /r",				Instruction::CPU_8086},
		{"CMP",				"r/m16,reg16",				"po 39 /r",				Instruction::CPU_8086},
		{"CMP",				"r/m32,reg32",				"po 39 /r",				Instruction::CPU_386},
		{"CMP",				"r/m64,reg64",				"po 39 /r",				Instruction::CPU_X64},
		{"CMP",				"reg8,r/m8",				"3A /r",				Instruction::CPU_8086},
		{"CMP",				"reg16,r/m16",				"po 3B /r",				Instruction::CPU_8086},
		{"CMP",				"reg32,r/m32",				"po 3B /r",				Instruction::CPU_386},
		{"CMP",				"reg64,r/m64",				"po 3B /r",				Instruction::CPU_X64},
		{"CMP",				"BYTE r/m8,imm8",			"80 /7 ib",				Instruction::CPU_8086},
		{"CMP",				"WORD r/m16,imm16",			"po 81 /7 iw",			Instruction::CPU_8086},
		{"CMP",				"DWORD r/m32,imm32",		"po 81 /7 id",			Instruction::CPU_386},
		{"CMP",				"QWORD r/m64,imm32",		"po 81 /7 id",			Instruction::CPU_X64},
		{"CMP",				"WORD r/m16,imm8",			"po 83 /7 ib",			Instruction::CPU_8086},
		{"CMP",				"DWORD r/m32,imm8",			"po 83 /7 ib",			Instruction::CPU_386},
		{"CMP",				"QWORD r/m64,imm8",			"po 83 /7 ib",			Instruction::CPU_X64},
		{"CMP",				"AL,imm8",					"3C ib",				Instruction::CPU_8086},
		{"CMP",				"AX,imm16",					"po 3D iw",				Instruction::CPU_8086},
		{"CMP",				"EAX,imm32",				"po 3D id",				Instruction::CPU_386},
		{"CMP",				"RAX,imm32",				"po 3D id",				Instruction::CPU_X64},
		{"CMPEQPD",			"xmmreg,r/m128",			"66 0F C2 /r 00",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPEQPS",			"xmmreg,r/m128",			"0F C2 /r 00",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPEQSD",			"xmmreg,xmm64",				"p2 0F C2 /r 00",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPEQSS",			"xmmreg,xmm32",				"p3 0F C2 /r 00",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPLEPD",			"xmmreg,r/m128",			"66 0F C2 /r 02",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPLEPS",			"xmmreg,r/m128",			"0F C2 /r 02",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPLESD",			"xmmreg,xmm64",				"p2 0F C2 /r 02",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPLESS",			"xmmreg,xmm32",				"p3 0F C2 /r 02",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPLTPD",			"xmmreg,r/m128",			"66 0F C2 /r 01",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPLTPS",			"xmmreg,r/m128",			"0F C2 /r 01",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPLTSD",			"xmmreg,xmm64",				"p2 0F C2 /r 01",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPLTSS",			"xmmreg,xmm32",				"p3 0F C2 /r 01",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPNEQPD",		"xmmreg,r/m128",			"66 0F C2 /r 04",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPNEQPS",		"xmmreg,r/m128",			"0F C2 /r 04",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPNEQSD",		"xmmreg,xmm64",				"p2 0F C2 /r 04",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPNEQSS",		"xmmreg,xmm32",				"p3 0F C2 /r 04",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPNLEPD",		"xmmreg,r/m128",			"66 0F C2 /r 06",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPNLEPS",		"xmmreg,r/m128",			"0F C2 /r 06",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPNLESD",		"xmmreg,xmm64",				"p2 0F C2 /r 06",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPNLESS",		"xmmreg,xmm32",				"p3 0F C2 /r 06",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPNLTPD",		"xmmreg,r/m128",			"66 0F C2 /r 05",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPNLTPS",		"xmmreg,r/m128",			"0F C2 /r 05",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPNLTSD",		"xmmreg,xmm64",				"p2 0F C2 /r 05",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPNLTSS",		"xmmreg,xmm32",				"p3 0F C2 /r 05",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPORDPD",		"xmmreg,r/m128",			"66 0F C2 /r 07",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPORDPS",		"xmmreg,r/m128",			"0F C2 /r 07",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPORDSD",		"xmmreg,xmm64",				"p2 0F C2 /r 07",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPORDSS",		"xmmreg,xmm32",				"p3 0F C2 /r 07",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPPD",			"xmmreg,r/m128,imm8",		"66 0F C2 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPPS",			"xmmreg,r/m128,imm8",		"0F C2 /r ib",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPSB",			"",							"A6",					Instruction::CPU_8086},
		{"CMPSD",			"",							"po A7",				Instruction::CPU_386},
		{"CMPSD",			"xmmreg,xmm64,imm8",		"p2 0F C2 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPSQ",			"",							"po A7",				Instruction::CPU_X64},
		{"CMPSS",			"xmmreg,xmm32,imm8",		"p3 0F C2 /r ib",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPSW",			"",							"po A7",				Instruction::CPU_8086},
		{"CMPUNORDPD",		"xmmreg,r/m128",			"66 0F C2 /r 03",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPUNORDPS",		"xmmreg,r/m128",			"0F C2 /r 03",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPUNORDSD",		"xmmreg,xmm64",				"p2 0F C2 /r 03",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CMPUNORDSS",		"xmmreg,xmm32",				"p3 0F C2 /r 03",		Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CMPXCHG",			"r/m8,reg8",				"0F B0 /r",				Instruction::CPU_PENTIUM},
		{"CMPXCHG",			"r/m16,reg16",				"po 0F B1 /r",			Instruction::CPU_PENTIUM},
		{"CMPXCHG",			"r/m32,reg32",				"po 0F B1 /r",			Instruction::CPU_PENTIUM},
		{"CMPXCHG",			"r/m64,reg64",				"po 0F B1 /r",			Instruction::CPU_X64},
	//	{"CMPXCHG486",		"r/m8,reg8",				"0F A6 /r",				Instruction::CPU_486 | Instruction::CPU_UNDOC},
	//	{"CMPXCHG486",		"r/m16,reg16",				"po 0F A7 /r",			Instruction::CPU_486 | Instruction::CPU_UNDOC},
	//	{"CMPXCHG486",		"r/m32,reg32",				"po 0F A7 /r",			Instruction::CPU_486 | Instruction::CPU_UNDOC},
		{"CMPXCHG16B",		"mem",						"0F C7 /1",				Instruction::CPU_X64},
		{"CMPXCHG8B",		"mem",						"0F C7 /1",				Instruction::CPU_PENTIUM},
		{"COMISD",			"xmmreg,xmm64",				"66 0F 2F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"COMISS",			"xmmreg,xmm32",				"0F 2F /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CPUID",			"",							"0F A2",				Instruction::CPU_PENTIUM},
		{"CQO",				"",							"po 99",				Instruction::CPU_X64},
		{"CVTDQ2PD",		"xmmreg,xmm64",				"p3 0F E6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTDQ2PS",		"xmmreg,r/m128",			"0F 5B /r",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPD2DQ",		"xmmreg,r/m128",			"p2 0F E6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPD2PI",		"mmreg,r/m128",				"66 0F 2D /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPD2PS",		"xmmreg,r/m128",			"66 0F 5A /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPI2PD",		"xmmreg,mm64",				"66 0F 2A /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPI2PS",		"xmmreg,mm64",				"0F 2A /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CVTPS2DQ",		"xmmreg,r/m128",			"66 0F 5B /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPS2PD",		"xmmreg,xmm64",				"0F 5A /r",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTPS2PI",		"mmreg,xmm64",				"0F 2D /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CVTSD2SI",		"reg32,xmm64",				"p2 0F 2D /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTSI2SD",		"xmmreg,r/m32",				"p2 0F 2A /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTSI2SS",		"xmmreg,r/m32",				"p3 0F 2A /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CVTSS2SD",		"xmmreg,xmm32",				"p3 0F 5A /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTSS2SI",		"reg32,xmm32",				"p3 0F 2D /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CVTTPD2DQ",		"xmmreg,r/m128",			"66 0F E6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTTPD2PI",		"mmreg,r/m128",				"66 0F 2C /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTTPS2DQ",		"xmmreg,r/m128",			"p3 0F 5B /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTTPS2PI",		"mmreg,xmm64",				"0F 2C /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CVTTSD2SI",		"reg32,xmm64",				"p2 0F 2C /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"CVTTSS2SI",		"reg32,xmm32",				"p3 0F 2C /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"CWD",				"",							"po 99",				Instruction::CPU_8086},
		{"CWDE",			"",							"po 98",				Instruction::CPU_386},
		{"DAA",				"",							"27",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"DAS",				"",							"2F",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"DB",				"",							"p1 ib"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DB",				"imm8",						"p1 ib"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DB",				"mem",						"p1 01"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DD",				"",							"p1 id"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DD",				"imm32",					"p1 id"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DD",				"mem",						"p1 04"},				// Special 'instruction', indicated by the 'p1' prefix
	//	{"DEC",				"reg16",					"po 48 +r",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"DEC",				"reg32",					"po 48 +r",				Instruction::CPU_386 | Instruction::CPU_INVALID64},
		{"DEC",				"BYTE r/m8",				"FE /1",				Instruction::CPU_8086},
		{"DEC",				"WORD r/m16",				"po FF /1",				Instruction::CPU_8086},
		{"DEC",				"DWORD r/m32",				"po FF /1",				Instruction::CPU_386},
		{"DEC",				"QWORD r/m64",				"po FF /1",				Instruction::CPU_X64},
		{"DIV",				"BYTE r/m8",				"F6 /6",				Instruction::CPU_8086},
		{"DIV",				"WORD r/m16",				"po F7 /6",				Instruction::CPU_8086},
		{"DIV",				"DWORD r/m32",				"po F7 /6",				Instruction::CPU_386},
		{"DIV",				"QWORD r/m64",				"po F7 /6",				Instruction::CPU_X64},
		{"DIVPD",			"xmmreg,r/m128",			"66 0F 5E /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"DIVPS",			"xmmreg,r/m128",			"0F 5E /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"DIVSD",			"xmmreg,xmm64",				"p2 0F 5E /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"DIVSS",			"xmmreg,xmm32",				"p3 0F 5E /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"DPPD",			"xmmreg,r/m128,imm8",		"66 0F 3A 41 /r ib",	Instruction::CPU_SSE4_1},
		{"DPPS",			"xmmreg,r/m128,imm8",		"66 0F 3A 40 /r ib",	Instruction::CPU_SSE4_1},
		{"DW",				"",							"p1 iw"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DW",				"imm16",					"p1 iw"},				// Special 'instruction', indicated by the 'p1' prefix
		{"DW",				"mem",						"p1 02"},				// Special 'instruction', indicated by the 'p1' prefix
		{"EMMS",			"",							"0F 77",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"EXTRACTPS",		"r/m32,xmmreg,imm8",		"66 0F 3A 17 /r ib",	Instruction::CPU_SSE4_1},
		{"EXTRACTPS",		"reg64,xmmreg,imm8",		"66 0F 3A 17 /r ib",	Instruction::CPU_SSE4_1 | Instruction::CPU_X64},
	//	{"ENTER",			"imm,imm",					"C8 iw ib",				Instruction::CPU_186},
		{"F2XM1",			"",							"D9 F0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FABS",			"",							"D9 E1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADD",			"DWORD mem32",				"D8 /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADD",			"QWORD mem64",				"DC /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADD",			"fpureg",					"D8 C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADD",			"ST0,fpureg",				"D8 C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FADD",			"TO fpureg",				"DC C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADD",			"fpureg,ST0",				"DC C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADDP",			"",							"DE C1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADDP",			"fpureg",					"DE C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FADDP",			"fpureg,ST0",				"DE C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FBLD",			"mem80",					"DF /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FBSTP",			"mem80",					"DF /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCHS",			"",							"D9 E0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCLEX",			"",							"9B DB E2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCMOVB",			"fpureg",					"DA C0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVB",			"ST0,fpureg",				"DA C0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVBE",			"fpureg",					"DA D0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVBE",			"ST0,fpureg",				"DA D0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVE",			"fpureg",					"DA C8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVE",			"ST0,fpureg",				"DA C8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNB",			"fpureg",					"DB C0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNB",			"ST0,fpureg",				"DB C0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNBE",		"fpureg",					"DB D0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNBE",		"ST0,fpureg",				"DB D0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNE",			"fpureg",					"DB C8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNE",			"ST0,fpureg",				"DB C8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNU",			"fpureg",					"DB D8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVNU",			"ST0,fpureg",				"DB D8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVU",			"fpureg",					"DA D8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCMOVU",			"ST0,fpureg",				"DA D8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCOM",			"DWORD mem32",				"D8 /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOM",			"QWORD mem64",				"DC /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOM",			"fpureg",					"D8 D0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOM",			"ST0,fpureg",				"D8 D0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOMI",			"fpureg",					"DB F0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCOMI",			"ST0,fpureg",				"DB F0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCOMIP",			"fpureg",					"DF F0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCOMIP",			"ST0,fpureg",				"DF F0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FCOMP",			"DWORD mem32",				"D8 /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOMP",			"QWORD mem64",				"DC /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOMP",			"fpureg",					"D8 D8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOMP",			"ST0,fpureg",				"D8 D8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOMPP",			"",							"DE D9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FCOS",			"",							"D9 FF",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FDECSTP",			"",							"D9 F6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDISI",			"",							"9B DB E1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIV",			"DWORD mem32",				"D8 /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIV",			"QWORD mem64",				"DC /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIV",			"fpureg",					"D8 F0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIV",			"ST0,fpureg",				"D8 F0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FDIV",			"TO fpureg",				"DC F8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIV",			"fpureg,ST0",				"DC F8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVP",			"",							"DE F9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVP",			"fpureg",					"DE F8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVP",			"fpureg,ST0",				"DE F8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVR",			"DWORD mem32",				"D8 /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVR",			"QWORD mem64",				"DC /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVR",			"fpureg",					"D8 F8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVR",			"ST0,fpureg",				"D8 F8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FDIVR",			"TO fpureg",				"DC F0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVR",			"fpureg,ST0",				"DC F0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVRP",			"",							"DE F1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVRP",			"fpureg",					"DE F0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FDIVRP",			"fpureg,ST0",				"DE F0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FEMMS",			"",							"0F 0E",				Instruction::CPU_3DNOW},
		{"FENI",			"",							"9B DB E0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FFREE",			"fpureg",					"DD C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FFREEP",			"fpureg",					"DF C0 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU | Instruction::CPU_UNDOC},
		{"FIADD",			"WORD mem16",				"DE /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIADD",			"DWORD mem32",				"DA /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FICOM",			"WORD mem16",				"DE /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FICOM",			"DWORD mem32",				"DA /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FICOMP",			"WORD mem16",				"DE /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FICOMP",			"DWORD mem32",				"DA /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIDIV",			"WORD mem16",				"DE /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIDIV",			"DWORD mem32",				"DA /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIDIVR",			"WORD mem16",				"DE /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIDIVR",			"DWORD mem32",				"DA /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FILD",			"WORD mem16",				"DF /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FILD",			"DWORD mem32",				"DB /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FILD",			"QWORD mem64",				"DF /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIMUL",			"WORD mem16",				"DE /1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIMUL",			"DWORD mem32",				"DA /1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FINCSTP",			"",							"D9 F7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FINIT",			"",							"9B DB E3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIST",			"WORD mem16",				"DF /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FIST",			"DWORD mem32",				"DB /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISTP",			"WORD mem16",				"DF /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISTP",			"DWORD mem32",				"DB /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISTP",			"QWORD mem64",				"DF /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISTTP",			"WORD mem16",				"DF /1",				Instruction::CPU_PNI},
		{"FISTTP",			"DWORD mem32",				"DB /1",				Instruction::CPU_PNI},
		{"FISTTP",			"QWORD mem64",				"DD /1",				Instruction::CPU_PNI},
		{"FISUB",			"WORD mem16",				"DE /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISUB",			"DWORD mem32",				"DA /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISUBR",			"WORD mem16",				"DE /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FISUBR",			"DWORD mem32",				"DA /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLD",				"DWORD mem32",				"D9 /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLD",				"QWORD mem64",				"DD /0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FLD",				"mem80",					"DB /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLD",				"fpureg",					"D9 C0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLD1",			"",							"D9 E8",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDCW",			"mem16",					"D9 /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDENV",			"mem",						"D9 /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDL2E",			"",							"D9 EA",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDL2T",			"",							"D9 E9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDLG2",			"",							"D9 EC",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDLN2",			"",							"D9 ED",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDPI",			"",							"D9 EB",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FLDZ",			"",							"D9 EE",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMUL",			"DWORD mem32",				"D8 /1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMUL",			"QWORD mem64",				"DC /1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMUL",			"",							"D8 C9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMUL",			"fpureg",					"D8 C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMUL",			"ST0,fpureg",				"D8 C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FMUL",			"TO fpureg",				"DC C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMUL",			"fpureg,ST0",				"DC C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMULP",			"fpureg",					"DE C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMULP",			"fpureg,ST0",				"DE C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FMULP",			"",							"DE C9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNCLEX",			"",							"DB E2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNDISI",			"",							"DB E1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNENI",			"",							"DB E0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNINIT",			"",							"DB E3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNOP",			"",							"D9 D0",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNSAVE",			"mem",						"DD /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNSTCW",			"mem16",					"D9 /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNSTENV",			"mem",						"D9 /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNSTSW",			"mem16",					"DD /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FNSTSW",			"AX",						"DF E0",				Instruction::CPU_286 | Instruction::CPU_FPU},
		{"FPATAN",			"",							"D9 F3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FPREM",			"",							"D9 F8",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FPREM1",			"",							"D9 F5",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FPTAN",			"",							"D9 F2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FRNDINT",			"",							"D9 FC",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FRSTOR",			"mem",						"DD /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSAVE",			"mem",						"9B DD /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSCALE",			"",							"D9 FD",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSETPM",			"",							"DB E4",				Instruction::CPU_286 | Instruction::CPU_FPU},
		{"FSIN",			"",							"D9 FE",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FSINCOS",			"",							"D9 FB",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FSQRT",			"",							"D9 FA",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FST",				"DWORD mem32",				"D9 /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FST",				"QWORD mem64",				"DD /2",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FST",				"fpureg",					"DD D0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTCW",			"mem16",					"9B D9 /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTENV",			"mem",						"9B D9 /6",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTP",			"DWORD mem32",				"D9 /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTP",			"QWORD mem64",				"DD /3",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FSTP",			"mem80",					"DB /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTP",			"fpureg",					"DD D8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTSW",			"mem16",					"9B DD /7",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSTSW",			"AX",						"9B DF E0",				Instruction::CPU_286 | Instruction::CPU_FPU},
		{"FSUB",			"DWORD mem32",				"D8 /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUB",			"QWORD mem64",				"DC /4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUB",			"fpureg",					"D8 E0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUB",			"ST0,fpureg",				"D8 E0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FSUB",			"TO fpureg",				"DC E8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUB",			"fpureg,ST0",				"DC E8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBP",			"",							"DE E9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBP",			"fpureg",					"DE E8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBP",			"fpureg,ST0",				"DE E8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBR",			"DWORD mem32",				"D8 /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBR",			"QWORD mem64",				"DC /5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBR",			"fpureg",					"D8 E8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBR",			"ST0,fpureg",				"D8 E8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FSUBR",			"TO fpureg",				"DC E0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBR",			"fpureg,ST0",				"DC E0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBRP",			"",							"DE E1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBRP",			"fpureg",					"DE E0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FSUBRP",			"fpureg,ST0",				"DE E0 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FTST",			"",							"D9 E4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FUCOM",			"fpureg",					"DD E0 +r",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FUCOM",			"ST0,fpureg",				"DD E0 +r",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FUCOMI",			"fpureg",					"DB E8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FUCOMI",			"ST0,fpureg",				"DB E8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FUCOMIP",			"fpureg",					"DF E8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FUCOMIP",			"ST0,fpureg",				"DF E8 +r",				Instruction::CPU_P6 | Instruction::CPU_FPU},
		{"FUCOMP",			"fpureg",					"DD E8 +r",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FUCOMP",			"ST0,fpureg",				"DD E8 +r",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FUCOMPP",			"",							"DA E9",				Instruction::CPU_386 | Instruction::CPU_FPU},
		{"FWAIT",			"",							"9B",					Instruction::CPU_8086},
		{"FXAM",			"",							"D9 E5",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FXCH",			"",							"D9 C9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FXCH",			"fpureg",					"D9 C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FXCH",			"fpureg,ST0",				"D9 C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FXCH",			"ST0,fpureg",				"D9 C8 +r",				Instruction::CPU_8086 | Instruction::CPU_FPU},
	//	{"FXRSTOR",			"mem",						"0F AE /1",				Instruction::CPU_P6 | Instruction::CPU_SSE | Instruction::CPU_FPU},
	//	{"FXSAVE",			"mem",						"0F AE /0",				Instruction::CPU_P6 | Instruction::CPU_SSE | Instruction::CPU_FPU},
		{"FXTRACT",			"",							"D9 F4",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FYL2X",			"",							"D9 F1",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"FYL2XP1",			"",							"D9 F9",				Instruction::CPU_8086 | Instruction::CPU_FPU},
		{"HADDPD",			"xmmreg,r/m128",			"66 0F 7C /r",			Instruction::CPU_PNI},
		{"HADDPS",			"xmmreg,r/m128",			"p2 0F 7C /r",			Instruction::CPU_PNI},
		{"HLT",				"",							"F4",					Instruction::CPU_8086},
		{"HSUBPD",			"xmmreg,r/m128",			"66 0F 7D /r",			Instruction::CPU_PNI},
		{"HSUBPS",			"xmmreg,r/m128",			"p2 0F 7D /r",			Instruction::CPU_PNI},
	//	{"IBTS",			"r/m16,reg16",				"po 0F A7 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"IBTS",			"r/m32,reg32",				"po 0F A7 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
		{"IDIV",			"BYTE r/m8",				"F6 /7",				Instruction::CPU_8086},
		{"IDIV",			"WORD r/m16",				"po F7 /7",				Instruction::CPU_8086},
		{"IDIV",			"DWORD r/m32",				"po F7 /7",				Instruction::CPU_386},
		{"IDIV",			"QWORD r/m64",				"po F7 /7",				Instruction::CPU_X64},
		{"IMUL",			"BYTE r/m8",				"F6 /5",				Instruction::CPU_8086},
		{"IMUL",			"WORD r/m16",				"po F7 /5",				Instruction::CPU_8086},
		{"IMUL",			"DWORD r/m32",				"po F7 /5",				Instruction::CPU_386},
		{"IMUL",			"QWORD r/m64",				"po F7 /5",				Instruction::CPU_X64},
		{"IMUL",			"reg16,r/m16",				"po 0F AF /r",			Instruction::CPU_386},
		{"IMUL",			"reg32,r/m32",				"po 0F AF /r",			Instruction::CPU_386},
		{"IMUL",			"reg64,r/m64",				"po 0F AF /r",			Instruction::CPU_X64},
		{"IMUL",			"reg16,imm8",				"po 6B /r ib",			Instruction::CPU_286},
		{"IMUL",			"reg32,imm8",				"po 6B /r ib",			Instruction::CPU_386},
		{"IMUL",			"reg64,imm8",				"po 6B /r ib",			Instruction::CPU_X64},
		{"IMUL",			"reg16,imm16",				"po 69 /r iw",			Instruction::CPU_286},
		{"IMUL",			"reg32,imm32",				"po 69 /r id",			Instruction::CPU_386},
		{"IMUL",			"reg64,imm32",				"po 69 /r id",			Instruction::CPU_X64},
		{"IMUL",			"reg16,r/m16,imm8",			"po 6B /r ib",			Instruction::CPU_286},
		{"IMUL",			"reg32,r/m32,imm8",			"po 6B /r ib",			Instruction::CPU_386},
		{"IMUL",			"reg64,r/m64,imm8",			"po 6B /r ib",			Instruction::CPU_X64},
		{"IMUL",			"reg16,r/m16,imm16",		"po 69 /r iw",			Instruction::CPU_286},
		{"IMUL",			"reg32,r/m32,imm32",		"po 69 /r id",			Instruction::CPU_386},
		{"IMUL",			"reg64,r/m64,imm32",		"po 69 /r id",			Instruction::CPU_X64},
		{"IN",				"AL,imm8",					"E4 ib",				Instruction::CPU_8086},
		{"IN",				"AX,imm8",					"po E5 ib",				Instruction::CPU_8086},
		{"IN",				"EAX,imm8",					"po E5 ib",				Instruction::CPU_386},
		{"IN",				"AL,DX",					"EC",					Instruction::CPU_8086},
		{"IN",				"AX,DX",					"po ED",				Instruction::CPU_8086},
		{"IN",				"EAX,DX",					"po ED",				Instruction::CPU_386},
	//	{"INC",				"reg16",					"po 40 +r",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"INC",				"reg32",					"po 40 +r",				Instruction::CPU_386 | Instruction::CPU_INVALID64},
		{"INC",				"BYTE r/m8",				"FE /0",				Instruction::CPU_8086},
		{"INC",				"WORD r/m16",				"po FF /0",				Instruction::CPU_8086},
		{"INC",				"DWORD r/m32",				"po FF /0",				Instruction::CPU_386},
		{"INC",				"QWORD r/m64",				"po FF /0",				Instruction::CPU_X64},
		{"INSB",			"",							"6C",					Instruction::CPU_186},
		{"INSD",			"",							"po 6D",				Instruction::CPU_386},
		{"INSERTPS",		"xmmreg,r/m32,imm8",		"66 0F 3A 21 /r ib",	Instruction::CPU_SSE4_1},
		{"INSW",			"",							"po 6D",				Instruction::CPU_186},
	//	{"INT",				"imm8",						"CD ib",				Instruction::CPU_8086},
	//	{"INT1",			"",							"F1",					Instruction::CPU_P6 | Instruction::CPU_UNDOC},
	//	{"ICEBP",			"",							"F1",					Instruction::CPU_P6 | Instruction::CPU_UNDOC},
	//	{"INT01",			"",							"F1",					Instruction::CPU_P6 | Instruction::CPU_UNDOC},
		{"INT03",			"",							"CC",					Instruction::CPU_8086},
		{"INT3",			"",							"CC",					Instruction::CPU_8086},
		{"INTO",			"",							"CE",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"INVD",			"",							"0F 08",				Instruction::CPU_486},
	//	{"INVLPG",			"mem",						"0F 01 /7",				Instruction::CPU_486},
	//	{"IRET",			"",							"CF",					Instruction::CPU_8086},
	//	{"IRETW",			"",							"po CF",				Instruction::CPU_8086},
	//	{"IRETD",			"",							"po CF",				Instruction::CPU_386},
		{"JA",				"NEAR imm8",				"77 -b",				Instruction::CPU_8086},
		{"JA",				"imm",						"0F 87 -i",				Instruction::CPU_386},
		{"JAE",				"NEAR imm8",				"73 -b",				Instruction::CPU_8086},
		{"JAE",				"imm",						"0F 83 -i",				Instruction::CPU_386},
		{"JB",				"NEAR imm8",				"72 -b",				Instruction::CPU_8086},
		{"JB",				"imm",						"0F 82 -i",				Instruction::CPU_386},
		{"JBE",				"NEAR imm8",				"76 -b",				Instruction::CPU_8086},
		{"JBE",				"imm",						"0F 86 -i",				Instruction::CPU_386},
		{"JC",				"NEAR imm8",				"72 -b",				Instruction::CPU_8086},
		{"JC",				"imm",						"0F 82 -i",				Instruction::CPU_386},
		{"JCXZ",			"NEAR imm8",				"po E3 -b",				Instruction::CPU_8086},
		{"JE",				"NEAR imm8",				"74 -b",				Instruction::CPU_8086},
		{"JE",				"imm",						"0F 84 -i",				Instruction::CPU_386},
		{"JECXZ",			"NEAR imm8",				"po E3 -b",				Instruction::CPU_386},
		{"JG",				"NEAR imm8",				"7F -b",				Instruction::CPU_8086},
		{"JG",				"imm",						"0F 8F -i",				Instruction::CPU_386},
		{"JGE",				"NEAR imm8",				"7D -b",				Instruction::CPU_8086},
		{"JGE",				"imm",						"0F 8D -i",				Instruction::CPU_386},
		{"JL",				"NEAR imm8",				"7C -b",				Instruction::CPU_8086},
		{"JL",				"imm",						"0F 8C -i",				Instruction::CPU_386},
		{"JLE",				"NEAR imm8",				"7E -b",				Instruction::CPU_8086},
		{"JLE",				"imm",						"0F 8E -i",				Instruction::CPU_386},
		{"JMP",				"imm",						"E9 -i",				Instruction::CPU_8086},
		{"JMP",				"NEAR imm8",				"EB -b",				Instruction::CPU_8086},
	//	{"JMP",				"imm:imm16",				"po EA iw iw",			Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"JMP",				"imm:imm32",				"po EA id iw",			Instruction::CPU_386 | Instruction::CPU_INVALID64},
		{"JMP",				"mem",						"po FF /5",				Instruction::CPU_8086},
	//	{"JMP",				"FAR mem",					"po FF /5",				Instruction::CPU_386},
		{"JMP",				"WORD r/m16",				"po FF /4",				Instruction::CPU_8086},
		{"JMP",				"DWORD r/m32",				"po FF /4",				Instruction::CPU_386},
		{"JMP",				"QWORD r/m64",				"po FF /4",				Instruction::CPU_X64},
		{"JNA",				"NEAR imm8",				"76 -b",				Instruction::CPU_8086},
		{"JNA",				"imm",						"0F 86 -i",				Instruction::CPU_386},
		{"JNAE",			"NEAR imm8",				"72 -b",				Instruction::CPU_8086},
		{"JNAE",			"imm",						"0F 82 -i",				Instruction::CPU_386},
		{"JNB",				"NEAR imm8",				"73 -b",				Instruction::CPU_8086},
		{"JNB",				"imm",						"0F 83 -i",				Instruction::CPU_386},
		{"JNBE",			"NEAR imm8",				"77 -b",				Instruction::CPU_8086},
		{"JNBE",			"imm",						"0F 87 -i",				Instruction::CPU_386},
		{"JNC",				"NEAR imm8",				"73 -b",				Instruction::CPU_8086},
		{"JNC",				"imm",						"0F 83 -i",				Instruction::CPU_386},
		{"JNE",				"NEAR imm8",				"75 -b",				Instruction::CPU_8086},
		{"JNE",				"imm",						"0F 85 -i",				Instruction::CPU_386},
		{"JNG",				"NEAR imm8",				"7E -b",				Instruction::CPU_8086},
		{"JNG",				"imm",						"0F 8E -i",				Instruction::CPU_386},
		{"JNGE",			"NEAR imm8",				"7C -b",				Instruction::CPU_8086},
		{"JNGE",			"imm",						"0F 8C -i",				Instruction::CPU_386},
		{"JNL",				"NEAR imm8",				"7D -b",				Instruction::CPU_8086},
		{"JNL",				"imm",						"0F 8D -i",				Instruction::CPU_386},
		{"JNLE",			"NEAR imm8",				"7F -b",				Instruction::CPU_8086},
		{"JNLE",			"imm",						"0F 8F -i",				Instruction::CPU_386},
		{"JNO",				"NEAR imm8",				"71 -b",				Instruction::CPU_8086},
		{"JNO",				"imm",						"0F 81 -i",				Instruction::CPU_386},
		{"JNP",				"NEAR imm8",				"7B -b",				Instruction::CPU_8086},
		{"JNP",				"imm",						"0F 8B -i",				Instruction::CPU_386},
		{"JNS",				"NEAR imm8",				"79 -b",				Instruction::CPU_8086},
		{"JNS",				"imm",						"0F 89 -i",				Instruction::CPU_386},
		{"JNZ",				"NEAR imm8",				"75 -b",				Instruction::CPU_8086},
		{"JNZ",				"imm",						"0F 85 -i",				Instruction::CPU_386},
		{"JO",				"NEAR imm8",				"70 -b",				Instruction::CPU_8086},
		{"JO",				"imm",						"0F 80 -i",				Instruction::CPU_386},
		{"JP",				"NEAR imm8",				"7A -b",				Instruction::CPU_8086},
		{"JP",				"imm",						"0F 8A -i",				Instruction::CPU_386},
		{"JPE",				"NEAR imm8",				"7A -b",				Instruction::CPU_8086},
		{"JPE",				"imm",						"0F 8A -i",				Instruction::CPU_386},
		{"JPO",				"NEAR imm8",				"7B -b",				Instruction::CPU_8086},
		{"JPO",				"imm",						"0F 8B -i",				Instruction::CPU_386},
		{"JRCXZ",			"NEAR imm8",				"po E3 -b",				Instruction::CPU_X64},
		{"JS",				"NEAR imm8",				"78 -b",				Instruction::CPU_8086},
		{"JS",				"imm",						"0F 88 -i",				Instruction::CPU_386},
		{"JZ",				"NEAR imm8",				"74 -b",				Instruction::CPU_8086},
		{"JZ",				"imm",						"0F 84 -i",				Instruction::CPU_386},
		{"LAHF",			"",							"9F",					Instruction::CPU_8086},
	//	{"LAR",				"reg16,r/m16",				"po 0F 02 /r",			Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LAR",				"reg32,r/m32",				"po 0F 02 /r",			Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"LDDQU",			"xmmreg,mem",				"p2 0F F0 /r",			Instruction::CPU_PNI},
		{"LDMXCSR",			"mem32",					"0F AE /2",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"LDS",				"reg16,mem",				"po C5 /r",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"LDS",				"reg32,mem",				"po C5 /r",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"LEA",				"reg16,mem",				"po 8D /r",				Instruction::CPU_8086},
		{"LEA",				"reg32,mem",				"po 8D /r",				Instruction::CPU_386},
		{"LEA",				"reg64,mem",				"po 8D /r",				Instruction::CPU_X64},
		{"LEAVE",			"",							"C9",					Instruction::CPU_186},
		{"LES",				"reg16,mem",				"po C4 /r",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"LES",				"reg32,mem",				"po C4 /r",				Instruction::CPU_8086 | Instruction::CPU_INVALID64},
		{"LFENCE",			"",							"0F AE E8",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"LFS",				"reg16,mem",				"po 0F B4 /r",			Instruction::CPU_386},
		{"LFS",				"reg32,mem",				"po 0F B4 /r",			Instruction::CPU_386},
		{"LGS",				"reg16,mem",				"po 0F B5 /r",			Instruction::CPU_386},
		{"LGS",				"reg32,mem",				"po 0F B5 /r",			Instruction::CPU_386},
	//	{"LGDT",			"mem",						"0F 01 /2",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LIDT",			"mem",						"0F 01 /3",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LLDT",			"r/m16",					"0F 00 /2",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LMSW",			"r/m16",					"0F 01 /6",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LOADALL",			"",							"0F 07",				Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"LOADALL286",		"",							"0F 05",				Instruction::CPU_286 | Instruction::CPU_UNDOC},
		{"LOCK ADC",		"mem8,reg8",				"p0 10 /r",				Instruction::CPU_8086},
		{"LOCK ADC",		"mem16,reg16",				"p0 po 11 /r",			Instruction::CPU_8086},
		{"LOCK ADC",		"mem32,reg32",				"p0 po 11 /r",			Instruction::CPU_386},
		{"LOCK ADC",		"BYTE mem8,imm8",			"p0 80 /2 ib",			Instruction::CPU_8086},
		{"LOCK ADC",		"WORD mem16,imm16",			"p0 po 81 /2 iw",		Instruction::CPU_8086},
		{"LOCK ADC",		"DWORD mem32,imm32",		"p0 po 81 /2 id",		Instruction::CPU_386},
		{"LOCK ADC",		"WORD mem16,imm8",			"p0 po 83 /2 ib",		Instruction::CPU_8086},
		{"LOCK ADC",		"DWORD mem32,imm8",			"p0 po 83 /2 ib",		Instruction::CPU_386},
		{"LOCK ADD",		"mem8,reg8",				"p0 00 /r",				Instruction::CPU_8086},
		{"LOCK ADD",		"mem16,reg16",				"p0 po 01 /r",			Instruction::CPU_8086},
		{"LOCK ADD",		"mem32,reg32",				"p0 po 01 /r",			Instruction::CPU_386},
		{"LOCK ADD",		"BYTE mem8,imm8",			"p0 80 /0 ib",			Instruction::CPU_8086},
		{"LOCK ADD",		"WORD mem16,imm16",			"p0 po 81 /0 iw",		Instruction::CPU_8086},
		{"LOCK ADD",		"DWORD mem32,imm32",		"p0 po 81 /0 id",		Instruction::CPU_386},
		{"LOCK ADD",		"WORD mem16,imm8",			"p0 po 83 /0 ib",		Instruction::CPU_8086},
		{"LOCK ADD",		"DWORD mem32,imm8",			"p0 po 83 /0 ib",		Instruction::CPU_386},
		{"LOCK AND",		"mem8,reg8",				"p0 20 /r",				Instruction::CPU_8086},
		{"LOCK AND",		"mem16,reg16",				"p0 po 21 /r",			Instruction::CPU_8086},
		{"LOCK AND",		"mem32,reg32",				"p0 po 21 /r",			Instruction::CPU_386},
		{"LOCK AND",		"BYTE mem8,imm8",			"80 /4 ib",				Instruction::CPU_8086},
		{"LOCK AND",		"WORD mem16,imm16",			"p0 po 81 /4 iw",		Instruction::CPU_8086},
		{"LOCK AND",		"DWORD mem32,imm32",		"p0 po 81 /4 id",		Instruction::CPU_386},
		{"LOCK AND",		"WORD mem16,imm8",			"p0 po 83 /4 ib",		Instruction::CPU_8086},
		{"LOCK AND",		"DWORD mem32,imm8",			"p0 po 83 /4 ib",		Instruction::CPU_386},
		{"LOCK BTC",		"mem16,reg16",				"p0 po 0F BB /r",		Instruction::CPU_386},
		{"LOCK BTC",		"mem32,reg32",				"p0 po 0F BB /r",		Instruction::CPU_386},
		{"LOCK BTC",		"WORD mem16,imm8",			"p0 po 0F BA /7 ib",	Instruction::CPU_386},
		{"LOCK BTC",		"DWORD mem32,imm8",			"p0 po 0F BA /7 ib",	Instruction::CPU_386},
		{"LOCK BTR",		"mem16,reg16",				"p0 po 0F B3 /r",		Instruction::CPU_386},
		{"LOCK BTR",		"mem32,reg32",				"p0 po 0F B3 /r",		Instruction::CPU_386},
		{"LOCK BTR",		"WORD mem16,imm8",			"p0 po 0F BA /6 ib",	Instruction::CPU_386},
		{"LOCK BTR",		"DWORD mem32,imm8",			"p0 po 0F BA /6 ib",	Instruction::CPU_386},
		{"LOCK BTS",		"mem16,reg16",				"p0 po 0F AB /r",		Instruction::CPU_386},
		{"LOCK BTS",		"mem32,reg32",				"p0 po 0F AB /r",		Instruction::CPU_386},
		{"LOCK BTS",		"WORD mem16,imm8",			"p0 po 0F BA /5 ib",	Instruction::CPU_386},
		{"LOCK BTS",		"DWORD mem32,imm8",			"p0 po 0F BA /5 ib",	Instruction::CPU_386},
		{"LOCK CMPXCHG",	"mem8,reg8",				"p0 0F B0 /r",			Instruction::CPU_PENTIUM},
		{"LOCK CMPXCHG",	"mem16,reg16",				"p0 po 0F B1 /r",		Instruction::CPU_PENTIUM},
		{"LOCK CMPXCHG",	"mem32,reg32",				"p0 po 0F B1 /r",		Instruction::CPU_PENTIUM},
		{"LOCK CMPXCHG8B",	"mem",						"p0 0F C7 /1",			Instruction::CPU_PENTIUM},
		{"LOCK DEC",		"BYTE mem8",				"p0 FE /1",				Instruction::CPU_8086},
		{"LOCK DEC",		"WORD mem16",				"p0 po FF /1",			Instruction::CPU_8086},
		{"LOCK DEC",		"DWORD mem32",				"p0 po FF /1",			Instruction::CPU_386},
		{"LOCK INC",		"BYTE mem8",				"p0 FE /0",				Instruction::CPU_8086},
		{"LOCK INC",		"WORD mem16",				"p0 po FF /0",			Instruction::CPU_8086},
		{"LOCK INC",		"DWORD mem32",				"p0 po FF /0",			Instruction::CPU_386},
		{"LOCK NEG",		"BYTE mem8",				"p0 F6 /3",				Instruction::CPU_8086},
		{"LOCK NEG",		"WORD mem16",				"p0 po F7 /3",			Instruction::CPU_8086},
		{"LOCK NEG",		"DWORD mem32",				"p0 po F7 /3",			Instruction::CPU_386},
		{"LOCK NOT",		"BYTE mem8",				"p0 F6 /2",				Instruction::CPU_8086},
		{"LOCK NOT",		"WORD mem16",				"p0 po F7 /2",			Instruction::CPU_8086},
		{"LOCK NOT",		"DWORD mem32",				"p0 po F7 /2",			Instruction::CPU_386},
		{"LOCK OR",			"mem8,reg8",				"p0 08 /r",				Instruction::CPU_8086},
		{"LOCK OR",			"mem16,reg16",				"p0 po 09 /r",			Instruction::CPU_8086},
		{"LOCK OR",			"mem32,reg32",				"p0 po 09 /r",			Instruction::CPU_386},
		{"LOCK OR",			"BYTE mem8,imm8",			"p0 80 /1 ib",			Instruction::CPU_8086},
		{"LOCK OR",			"WORD mem16,imm16",			"p0 po 81 /1 iw",		Instruction::CPU_8086},
		{"LOCK OR",			"DWORD mem32,imm32",		"p0 po 81 /1 id",		Instruction::CPU_386},
		{"LOCK OR",			"WORD mem16,imm8",			"p0 po 83 /1 ib",		Instruction::CPU_8086},
		{"LOCK OR",			"DWORD mem32,imm8",			"p0 po 83 /1 ib",		Instruction::CPU_386},
		{"LOCK SBB",		"mem8,reg8",				"p0 18 /r",				Instruction::CPU_8086},
		{"LOCK SBB",		"mem16,reg16",				"p0 po 19 /r",			Instruction::CPU_8086},
		{"LOCK SBB",		"mem32,reg32",				"p0 po 19 /r",			Instruction::CPU_386},
		{"LOCK SBB",		"BYTE mem8,imm8",			"p0 80 /3 ib",			Instruction::CPU_8086},
		{"LOCK SBB",		"WORD mem16,imm16",			"p0 po 81 /3 iw",		Instruction::CPU_8086},
		{"LOCK SBB",		"DWORD mem32,imm32",		"p0 po 81 /3 id",		Instruction::CPU_386},
		{"LOCK SBB",		"WORD mem16,imm8",			"p0 po 83 /3 ib",		Instruction::CPU_8086},
		{"LOCK SBB",		"DWORD mem32,imm8",			"p0 po 83 /3 ib",		Instruction::CPU_8086},
		{"LOCK SUB",		"BYTE mem8,imm8",			"p0 80 /5 ib",			Instruction::CPU_8086},
		{"LOCK SUB",		"WORD mem16,imm16",			"p0 po 81 /5 iw",		Instruction::CPU_8086},
		{"LOCK SUB",		"DWORD mem32,imm32",		"p0 po 81 /5 id",		Instruction::CPU_386},
		{"LOCK SUB",		"WORD mem16,imm8",			"p0 po 83 /5 ib",		Instruction::CPU_8086},
		{"LOCK SUB",		"DWORD mem32,imm8",			"p0 po 83 /5 ib",		Instruction::CPU_386},
		{"LOCK SUB",		"mem8,reg8",				"p0 28 /r",				Instruction::CPU_8086},
		{"LOCK SUB",		"mem16,reg16",				"p0 po 29 /r",			Instruction::CPU_8086},
		{"LOCK SUB",		"mem32,reg32",				"p0 po 29 /r",			Instruction::CPU_386},
		{"LOCK XADD",		"mem8,reg8",				"p0 0F C0 /r",			Instruction::CPU_486},
		{"LOCK XADD",		"mem16,reg16",				"p0 po 0F C1 /r",		Instruction::CPU_486},
		{"LOCK XADD",		"mem32,reg32",				"p0 po 0F C1 /r",		Instruction::CPU_486},
		{"LOCK XCHG",		"mem8,reg8",				"p0 86 /r",				Instruction::CPU_8086},
		{"LOCK XCHG",		"mem16,reg16",				"p0 po 87 /r",			Instruction::CPU_8086},
		{"LOCK XCHG",		"mem32,reg32",				"p0 po 87 /r",			Instruction::CPU_386},
		{"LOCK XOR",		"mem8,reg8",				"p0 30 /r",				Instruction::CPU_8086},
		{"LOCK XOR",		"mem16,reg16",				"p0 po 31 /r",			Instruction::CPU_8086},
		{"LOCK XOR",		"mem32,reg32",				"p0 po 31 /r",			Instruction::CPU_386},
		{"LOCK XOR",		"BYTE mem8,imm8",			"p0 80 /6 ib",			Instruction::CPU_8086},
		{"LOCK XOR",		"WORD mem16,imm16",			"p0 po 81 /6 iw",		Instruction::CPU_8086},
		{"LOCK XOR",		"DWORD mem32,imm32",		"p0 po 81 /6 id",		Instruction::CPU_386},
		{"LOCK XOR",		"WORD mem16,imm8",			"p0 po 83 /6 ib",		Instruction::CPU_8086},
		{"LOCK XOR",		"DWORD mem32,imm8",			"p0 po 83 /6 ib",		Instruction::CPU_386},
		{"LODSB",			"",							"AC",					Instruction::CPU_8086},
		{"LODSD",			"",							"po AD",				Instruction::CPU_386},
		{"LODSQ",			"",							"po AD",				Instruction::CPU_X64},
		{"LODSW",			"",							"po AD",				Instruction::CPU_8086},
		{"LOOP",			"imm",						"E2 -b",				Instruction::CPU_8086},
		{"LOOP",			"imm,CX",					"pa E2 -b",				Instruction::CPU_8086},
		{"LOOP",			"imm,ECX",					"pa E2 -b",				Instruction::CPU_386},
		{"LOOPE",			"imm",						"E1 -b",				Instruction::CPU_8086},
		{"LOOPE",			"imm,CX",					"pa E1 -b",				Instruction::CPU_8086},
		{"LOOPE",			"imm,ECX",					"pa E1 -b",				Instruction::CPU_386},
		{"LOOPNE",			"imm",						"E0 -b",				Instruction::CPU_8086},
		{"LOOPNE",			"imm,CX",					"pa E0 -b",				Instruction::CPU_8086},
		{"LOOPNE",			"imm,ECX",					"pa E0 -b",				Instruction::CPU_386},
		{"LOOPNZ",			"imm",						"E0 -b",				Instruction::CPU_8086},
		{"LOOPNZ",			"imm,CX",					"pa E0 -b",				Instruction::CPU_8086},
		{"LOOPNZ",			"imm,ECX",					"pa E0 -b",				Instruction::CPU_386},
		{"LOOPZ",			"imm",						"E1 -b",				Instruction::CPU_8086},
		{"LOOPZ",			"imm,CX",					"pa E1 -b",				Instruction::CPU_8086},
		{"LOOPZ",			"imm,ECX",					"pa E1 -b",				Instruction::CPU_386},
	//	{"LSL",				"reg16,r/m16",				"po 0F 03 /r",			Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LSL",				"reg32,r/m32",				"po 0F 03 /r",			Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"LTR",				"r/m16",					"0F 00 /3",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"LSS",				"reg16,mem",				"po 0F B2 /r",			Instruction::CPU_386},
		{"LSS",				"reg32,mem",				"po 0F B2 /r",			Instruction::CPU_386},
		{"MASKMOVDQU",		"xmmreg,xmmreg",			"66 0F F7 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MASKMOVQ",		"mmreg,mmreg",				"0F F7 /r",				Instruction::CPU_KATMAI},
		{"MAXPD",			"xmmreg,r/m128",			"66 0F 5F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MAXPS",			"xmmreg,r/m128",			"0F 5F /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MAXSD",			"xmmreg,xmm64",				"p2 0F 5F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MAXSS",			"xmmreg,xmm32",				"p3 0F 5F /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MFENCE",			"",							"0F AE F0",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MINPD",			"xmmreg,r/m128",			"66 0F 5D /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MINPS",			"xmmreg,r/m128",			"0F 5D /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MINSD",			"xmmreg,xmm64",				"p2 0F 5D /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MINSS",			"xmmreg,xmm32",				"p3 0F 5D /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MONITOR",			"",							"0F 01 C8",				Instruction::CPU_PNI},
		{"MOV",				"r/m8,reg8",				"88 /r",				Instruction::CPU_8086},
		{"MOV",				"r/m16,reg16",				"po 89 /r",				Instruction::CPU_8086},
		{"MOV",				"r/m32,reg32",				"po 89 /r",				Instruction::CPU_386},
		{"MOV",				"r/m64,reg64",				"po 89 /r",				Instruction::CPU_X64},
		{"MOV",				"reg8,r/m8",				"8A /r",				Instruction::CPU_8086},
		{"MOV",				"reg16,r/m16",				"po 8B /r",				Instruction::CPU_8086},
		{"MOV",				"reg32,r/m32",				"po 8B /r",				Instruction::CPU_386},
		{"MOV",				"reg64,r/m64",				"po 8B /r",				Instruction::CPU_X64},
		{"MOV",				"reg8,imm8",				"B0 +r ib",				Instruction::CPU_8086},
		{"MOV",				"reg16,imm16",				"po B8 +r iw",			Instruction::CPU_8086},
		{"MOV",				"reg32,imm32",				"po B8 +r id",			Instruction::CPU_386},
	//	{"MOV",				"reg64,imm64",				"po B8 +r iq",			Instruction::CPU_X64},   // FIXME: imm64 unimplemented
		{"MOV",				"BYTE r/m8,imm8",			"C6 /0 ib",				Instruction::CPU_8086},
		{"MOV",				"WORD r/m16,imm16",			"po C7 /0 iw",			Instruction::CPU_8086},
		{"MOV",				"DWORD r/m32,imm32",		"po C7 /0 id",			Instruction::CPU_386},
		{"MOV",				"QWORD r/m64,imm32",		"po C7 /0 id",			Instruction::CPU_X64},
	//	{"MOV",				"AL,memoffs8",				"A0 id",				Instruction::CPU_8086},
	//	{"MOV",				"AX,memoffs16",				"po A1 id",				Instruction::CPU_8086},
	//	{"MOV",				"EAX,memoffs32",			"po A1 id",				Instruction::CPU_386},
	//	{"MOV",				"memoffs8,AL",				"A2 id",				Instruction::CPU_8086},
	//	{"MOV",				"memoffs16,AX",				"po A3 id",				Instruction::CPU_8086},
	//	{"MOV",				"memoffs32,EAX",			"po A3 id",				Instruction::CPU_386},
	//	{"MOV",				"r/m16,segreg",				"po 8C /r",				Instruction::CPU_8086},
	//	{"MOV",				"r/m32,segreg",				"po 8C /r",				Instruction::CPU_386},
	//	{"MOV",				"segreg,r/m16",				"po 8E /r",				Instruction::CPU_8086},
	//	{"MOV",				"segreg,r/m32",				"po 8E /r",				Instruction::CPU_386},
	//	{"MOV",				"reg32,CR",					"0F 20 /r",				Instruction::CPU_386},
	//	{"MOV",				"reg32,DR",					"0F 21 /r",				Instruction::CPU_386},
	//	{"MOV",				"reg32,TR",					"0F 24 /r",				Instruction::CPU_386},
	//	{"MOV",				"CR,reg32",					"0F 22 /r",				Instruction::CPU_386},
	//	{"MOV",				"DR,reg32",					"0F 23 /r",				Instruction::CPU_386},
	//	{"MOV",				"TR,reg32",					"0F 26 /r",				Instruction::CPU_386},
		{"MOVAPD",			"xmmreg,r/m128",			"66 0F 28 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVAPD",			"r/m128,xmmreg",			"66 0F 29 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVAPS",			"xmmreg,r/m128",			"0F 28 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVAPS",			"r/m128,xmmreg",			"0F 29 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVD",			"mmreg,r/m32",				"0F 6E /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"MOVD",			"mmreg,r/m64",				"0F 6E /r",				Instruction::CPU_X64},
		{"MOVD",			"r/m32,mmreg",				"0F 7E /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"MOVD",			"r/m64,mmreg",				"0F 7E /r",				Instruction::CPU_X64},
		{"MOVD",			"xmmreg,r/m32",				"66 0F 6E /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVD",			"xmmreg,r/m64",				"66 0F 6E /r",			Instruction::CPU_X64},
		{"MOVD",			"r/m32,xmmreg",				"66 0F 7E /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVD",			"r/m64,xmmreg",				"66 0F 7E /r",			Instruction::CPU_X64},
		{"MOVDDUP",			"xmmreg,r/m128",			"p2 0F 12 /r",			Instruction::CPU_PNI},
		{"MOVDQ2Q",			"mmreg,xmmreg",				"p2 0F D6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVDQA",			"xmmreg,r/m128",			"66 0F 6F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVDQA",			"r/m128,xmmreg",			"66 0F 7F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVDQU",			"xmmreg,r/m128",			"p3 0F 6F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVDQU",			"r/m128,xmmreg",			"p3 0F 7F /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVHLPS",			"xmmreg,xmmreg",			"0F 12 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVHPD",			"xmmreg,mem64",				"66 0F 16 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVHPD",			"mem64,xmmreg",				"66 0F 17 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVHPS",			"xmmreg,mem64",				"0F 16 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVHPS",			"mem64,xmmreg",				"0F 17 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVHPS",			"xmmreg,xmmreg",			"0F 16 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVLHPS",			"xmmreg,xmmreg",			"0F 16 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVLPD",			"xmmreg,mem64",				"66 0F 12 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVLPD",			"mem64,xmmreg",				"66 0F 13 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVLPS",			"xmmreg,mem64",				"0F 12 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVLPS",			"mem64,xmmreg",				"0F 13 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVMSKPD",		"reg32,xmmreg",				"66 0F 50 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVMSKPS",		"reg32,xmmreg",				"0F 50 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVNTDQ",			"mem128,xmmreg",			"66 0F E7 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVNTDQA",		"xmmreg,mem128",			"66 0F 38 2A /r",		Instruction::CPU_SSE4_1},
		{"MOVNTI",			"mem32,reg32",				"0F C3 /r",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVNTI",			"mem64,reg64",				"0F C3 /r",				Instruction::CPU_X64},
		{"MOVNTPD",			"mem128,xmmreg",			"66 0F 2B /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVNTPS",			"mem128,xmmreg",			"0F 2B /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVNTQ",			"mem64,mmreg",				"0F E7 /r",				Instruction::CPU_KATMAI},
		{"MOVQ",			"mmreg,mm64",				"0F 6F /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"MOVQ",			"mm64,mmreg",				"0F 7F /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"MOVQ",			"xmmreg,xmm64",				"p3 0F 7E /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVQ",			"xmm64,xmmreg",				"66 0F D6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVQ2DQ",			"xmmreg,mmreg",				"p3 0F D6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVSB",			"",							"A4",					Instruction::CPU_8086},
		{"MOVSD",			"",							"po A5",				Instruction::CPU_386},
		{"MOVSD",			"xmmreg,xmm64",				"p2 0F 10 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVSD",			"xmm64,xmmreg",				"p2 0F 11 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVSHDUP",		"xmmreg,r/m128",			"p3 0F 16 /r",			Instruction::CPU_PNI},
		{"MOVSLDUP",		"xmmreg,r/m128",			"p3 0F 12 /r",			Instruction::CPU_PNI},
		{"MOVSQ",			"",							"po A5",				Instruction::CPU_X64},
		{"MOVSS",			"xmmreg,xmm32",				"p3 0F 10 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVSS",			"xmm32,xmmreg",				"p3 0F 11 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVSW",			"",							"po A5",				Instruction::CPU_8086},
		{"MOVSX",			"reg16,r/m8",				"po 0F BE /r",			Instruction::CPU_386},
		{"MOVSX",			"reg32,r/m8",				"po 0F BE /r",			Instruction::CPU_386},
		{"MOVSX",			"reg64,r/m8",				"po 0F BE /r",			Instruction::CPU_X64},
		{"MOVSX",			"reg32,r/m16",				"po 0F BF /r",			Instruction::CPU_386},
		{"MOVSX",			"reg64,r/m16",				"po 0F BF /r",			Instruction::CPU_X64},
		{"MOVSXD",			"reg64,r/m32",				"po 63 /r",				Instruction::CPU_X64},
		{"MOVUPD",			"xmmreg,r/m128",			"66 0F 10 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVUPD",			"r/m128,xmmreg",			"66 0F 11 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MOVUPS",			"xmmreg,r/m128",			"0F 10 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVUPS",			"r/m128,xmmreg",			"0F 11 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MOVZX",			"reg16,r/m8",				"po 0F B6 /r",			Instruction::CPU_386},
		{"MOVZX",			"reg32,r/m8",				"po 0F B6 /r",			Instruction::CPU_386},
		{"MOVZX",			"reg64,r/m8",				"po 0F B6 /r",			Instruction::CPU_X64},
		{"MOVZX",			"reg32,r/m16",				"po 0F B7 /r",			Instruction::CPU_386},
		{"MOVZX",			"reg64,r/m16",				"po 0F B7 /r",			Instruction::CPU_X64},
		{"MPSADBW",			"xmmreg,r/m128,imm8",		"66 0F 3A 42 /r ib",	Instruction::CPU_SSE4_1},
		{"MUL",				"BYTE r/m8",				"F6 /4",				Instruction::CPU_8086},
		{"MUL",				"WORD r/m16",				"po F7 /4",				Instruction::CPU_8086},
		{"MUL",				"DWORD r/m32",				"po F7 /4",				Instruction::CPU_386},
		{"MUL",				"QWORD r/m64",				"po F7 /4",				Instruction::CPU_X64},
		{"MULPD",			"xmmreg,r/m128",			"66 0F 59 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MULPS",			"xmmreg,r/m128",			"0F 59 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MULSD",			"xmmreg,xmm64",				"p2 0F 59 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"MULSS",			"xmmreg,xmm32",				"p3 0F 59 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"MWAIT",			"",							"0F 01 C9",				Instruction::CPU_PNI},
		{"NEG",				"BYTE r/m8",				"F6 /3",				Instruction::CPU_8086},
		{"NEG",				"WORD r/m16",				"po F7 /3",				Instruction::CPU_8086},
		{"NEG",				"DWORD r/m32",				"po F7 /3",				Instruction::CPU_386},
		{"NEG",				"QWORD r/m64",				"po F7 /3",				Instruction::CPU_X64},
		{"NOP",				"",							"90",					Instruction::CPU_8086},
		{"NOT",				"BYTE r/m8",				"F6 /2",				Instruction::CPU_8086},
		{"NOT",				"WORD r/m16",				"po F7 /2",				Instruction::CPU_8086},
		{"NOT",				"DWORD r/m32",				"po F7 /2",				Instruction::CPU_386},
		{"NOT",				"QWORD r/m64",				"po F7 /2",				Instruction::CPU_X64},
		{"NULL",			"",							""},					// Empty 'instruction', placeholder for annotations
		{"OR",				"r/m8,reg8",				"08 /r",				Instruction::CPU_8086},
		{"OR",				"r/m16,reg16",				"po 09 /r",				Instruction::CPU_8086},
		{"OR",				"r/m32,reg32",				"po 09 /r",				Instruction::CPU_386},
		{"OR",				"r/m64,reg64",				"po 09 /r",				Instruction::CPU_X64},
		{"OR",				"reg8,r/m8",				"0A /r",				Instruction::CPU_8086},
		{"OR",				"reg16,r/m16",				"po 0B /r",				Instruction::CPU_8086},
		{"OR",				"reg32,r/m32",				"po 0B /r",				Instruction::CPU_386},
		{"OR",				"reg64,r/m64",				"po 0B /r",				Instruction::CPU_X64},
		{"OR",				"BYTE r/m8,imm8",			"80 /1 ib",				Instruction::CPU_8086},
		{"OR",				"WORD r/m16,imm16",			"po 81 /1 iw",			Instruction::CPU_8086},
		{"OR",				"DWORD r/m32,imm32",		"po 81 /1 id",			Instruction::CPU_386},
		{"OR",				"QWORD r/m64,imm32",		"po 81 /1 id",			Instruction::CPU_X64},
		{"OR",				"WORD r/m16,imm8",			"po 83 /1 ib",			Instruction::CPU_8086},
		{"OR",				"DWORD r/m32,imm8",			"po 83 /1 ib",			Instruction::CPU_386},
		{"OR",				"QWORD r/m64,imm8",			"po 83 /1 ib",			Instruction::CPU_X64},
		{"OR",				"AL,imm8",					"0C ib",				Instruction::CPU_8086},
		{"OR",				"AX,imm16",					"po 0D iw",				Instruction::CPU_8086},
		{"OR",				"EAX,imm32",				"po 0D id",				Instruction::CPU_386},
		{"OR",				"RAX,imm32",				"po 0D id",				Instruction::CPU_X64},
		{"ORPD",			"xmmreg,r/m128",			"66 0F 56 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"ORPS",			"xmmreg,r/m128",			"0F 56 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"OUT",				"imm8,AL",					"E6 ib",				Instruction::CPU_8086},
		{"OUT",				"imm8,AX",					"po E7 ib",				Instruction::CPU_8086},
		{"OUT",				"imm8,EAX",					"po E7 ib",				Instruction::CPU_386},
		{"OUT",				"DX,AL",					"EE",					Instruction::CPU_8086},
		{"OUT",				"DX,AX",					"po EF",				Instruction::CPU_8086},
		{"OUT",				"DX,EAX",					"po EF",				Instruction::CPU_386},
		{"OUTSB",			"",							"6E",					Instruction::CPU_186},
		{"OUTSD",			"",							"po 6F",				Instruction::CPU_386},
		{"OUTSW",			"",							"po 6F",				Instruction::CPU_186},
		{"PABSB",			"mmreg,mm64",				"0F 38 1c /r",			Instruction::CPU_SSSE3},
		{"PABSB",			"xmmreg,r/m128",			"66 0f 38 1c /r",		Instruction::CPU_SSSE3},
		{"PABSD",			"mmreg,mm64",				"0F 38 0a /r",			Instruction::CPU_SSSE3},
		{"PABSD",			"xmmreg,r/m128",			"66 0f 38 1e /r",		Instruction::CPU_SSSE3},
		{"PABSW",			"mmreg,mm64",				"0F 38 1e /r",			Instruction::CPU_SSSE3},
		{"PABSW",			"xmmreg,r/m128",			"66 0f 38 1d /r",		Instruction::CPU_SSSE3},
		{"PACKSSDW",		"mmreg,mm64",				"0F 6B /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PACKSSDW",		"xmmreg,r/m128",			"66 0F 6B /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PACKSSWB",		"mmreg,mm64",				"0F 63 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PACKSSWB",		"xmmreg,r/m128",			"66 0F 63 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PACKUSDW",		"xmmreg,r/m128",			"66 0F 38 2B /r",		Instruction::CPU_SSE4_1},
		{"PACKUSWB",		"mmreg,mm64",				"0F 67 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PACKUSWB",		"xmmreg,r/m128",			"66 0F 67 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDB",			"mmreg,mm64",				"0F FC /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDB",			"xmmreg,r/m128",			"66 0F FC /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDD",			"mmreg,mm64",				"0F FE /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDD",			"xmmreg,r/m128",			"66 0F FE /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDQ",			"mmreg,mm64",				"0F D4 /r",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDQ",			"xmmreg,r/m128",			"66 0F D4 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDSB",			"mmreg,mm64",				"0F EC /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDSB",			"xmmreg,r/m128",			"66 0F EC /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDSIW",			"mmreg,mm64",				"0F 51 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PADDSW",			"mmreg,mm64",				"0F ED /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDSW",			"xmmreg,r/m128",			"66 0F ED /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDUSB",			"mmreg,mm64",				"0F DC /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDUSB",			"xmmreg,r/m128",			"66 0F DC /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDUSW",			"mmreg,mm64",				"0F DD /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDUSW",			"xmmreg,r/m128",			"66 0F DD /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PADDW",			"mmreg,mm64",				"0F FD /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PADDW",			"xmmreg,r/m128",			"66 0F FD /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PALIGNR",			"mmreg,mm64,imm8",			"0F 3a 0f ib",			Instruction::CPU_SSSE3},
		{"PALIGNR",			"xmmreg,r/m128,imm8",		"66 0f 38 1c ib",		Instruction::CPU_SSSE3},
		{"PAND",			"mmreg,mm64",				"0F DB /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PAND",			"xmmreg,r/m128",			"66 0F DB /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PANDN",			"mmreg,mm64",				"0F DF /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PANDN",			"xmmreg,r/m128",			"66 0F DF /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PAUSE",			"",							"p3 90",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PAVEB",			"mmreg,mm64",				"0F 50 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PAVGB",			"mmreg,mm64",				"0F E0 /r",				Instruction::CPU_KATMAI},
		{"PAVGB",			"xmmreg,r/m128",			"66 0F E0 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PAVGUSB",			"mmreg,mm64",				"0F 0F /r BF",			Instruction::CPU_3DNOW},
		{"PAVGW",			"mmreg,mm64",				"0F E3 /r",				Instruction::CPU_KATMAI},
		{"PAVGW",			"xmmreg,r/m128",			"66 0F E3 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PBLENDVB",		"xmmreg,r/m128",			"66 0F 38 10 /r",		Instruction::CPU_SSE4_1},
		{"PBLENDW",			"xmmreg,r/m128,imm8",		"66 0F 3A 0E /r ib",	Instruction::CPU_SSE4_1},
		{"PCMPEQB",			"mmreg,mm64",				"0F 74 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PCMPEQB",			"xmmreg,r/m128",			"66 0F 74 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PCMPEQD",			"mmreg,mm64",				"0F 76 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PCMPEQD",			"xmmreg,r/m128",			"66 0F 76 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PCMPEQQ",			"xmmreg,r/m128",			"66 0F 38 29 /r",		Instruction::CPU_SSE4_1},
		{"PCMPEQW",			"mmreg,mm64",				"0F 75 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PCMPEQW",			"xmmreg,r/m128",			"66 0F 75 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PCMPESTRI",		"xmmreg,r/m128,imm8",		"66 0F 3A 61 /r ib",	Instruction::CPU_SSE4_2},
		{"PCMPESTRM",		"xmmreg,r/m128,imm8",		"66 0F 3A 60 /r ib",	Instruction::CPU_SSE4_2},
		{"PCMPGTB",			"mmreg,mm64",				"0F 64 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PCMPGTB",			"xmmreg,r/m128",			"66 0F 64 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PCMPGTD",			"mmreg,mm64",				"0F 66 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PCMPGTD",			"xmmreg,r/m128",			"66 0F 66 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PCMPGTQ",			"xmmreg,r/m128",			"66 0F 38 37 /r",		Instruction::CPU_SSE4_1},
		{"PCMPGTW",			"mmreg,mm64",				"0F 65 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PCMPGTW",			"xmmreg,r/m128",			"66 0F 65 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PCMPISTRI",		"xmmreg,r/m128,imm8",		"66 0F 3A 63 /r ib",	Instruction::CPU_SSE4_2},
		{"PCMPISTRM",		"xmmreg,r/m128,imm8",		"66 0F 3A 62 /r ib",	Instruction::CPU_SSE4_2},
		{"PDISTIB",			"mmreg,mem64",				"0F 54 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PEXTRB",			"reg32,xmmreg,imm8",		"66 0F 3A 14 /r ib",	Instruction::CPU_SSE4_1},
		{"PEXTRB",			"mem8,xmmreg,imm8",			"66 0F 3A 14 /r ib",	Instruction::CPU_SSE4_1},
		{"PEXTRB",			"reg64,xmmreg,imm8",		"66 0F 3A 14 /r ib",	Instruction::CPU_SSE4_1 | Instruction::CPU_X64},
		{"PEXTRD",			"r/m32,xmmreg,imm8",		"66 0F 3A 16 /r ib",	Instruction::CPU_SSE4_1},
		{"PEXTRD",			"r/m64,xmmreg,imm8",		"66 0F 3A 16 /r ib",	Instruction::CPU_SSE4_1 | Instruction::CPU_X64},
		{"PEXTRW",			"mem16,xmmreg,imm8",		"66 0F 3A 15 /r ib",	Instruction::CPU_SSE4_1},
		{"PEXTRW",			"reg64,xmmreg,imm8",		"66 0F 3A 15 /r ib",	Instruction::CPU_SSE4_1 | Instruction::CPU_X64},
		{"PEXTRW",			"reg32,mmreg,imm8",			"0F C5 /r ib",			Instruction::CPU_KATMAI},
		{"PEXTRW",			"reg32,xmmreg,imm8",		"66 0F C5 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PF2ID",			"mmreg,mm64",				"0F 0F /r 1D",			Instruction::CPU_3DNOW},
		{"PF2IW",			"mmreg,mm64",				"0F 0F /r 1C",			Instruction::CPU_ATHLON},
		{"PFACC",			"mmreg,mm64",				"0F 0F /r AE",			Instruction::CPU_3DNOW},
		{"PFADD",			"mmreg,mm64",				"0F 0F /r 9E",			Instruction::CPU_3DNOW},
		{"PFCMPEQ",			"mmreg,mm64",				"0F 0F /r B0",			Instruction::CPU_3DNOW},
		{"PFCMPGE",			"mmreg,mm64",				"0F 0F /r 90",			Instruction::CPU_3DNOW},
		{"PFCMPGT",			"mmreg,mm64",				"0F 0F /r A0",			Instruction::CPU_3DNOW},
		{"PFMAX",			"mmreg,mm64",				"0F 0F /r A4",			Instruction::CPU_3DNOW},
		{"PFMIN",			"mmreg,mm64",				"0F 0F /r 94",			Instruction::CPU_3DNOW},
		{"PFMUL",			"mmreg,mm64",				"0F 0F /r B4",			Instruction::CPU_3DNOW},
		{"PFNACC",			"mmreg,mm64",				"0F 0F /r 8A",			Instruction::CPU_ATHLON},
		{"PFPNACC",			"mmreg,mm64",				"0F 0F /r 8E",			Instruction::CPU_ATHLON},
		{"PFRCP",			"mmreg,mm64",				"0F 0F /r 96",			Instruction::CPU_3DNOW},
		{"PFRCPIT1",		"mmreg,mm64",				"0F 0F /r A6",			Instruction::CPU_3DNOW},
		{"PFRCPIT2",		"mmreg,mm64",				"0F 0F /r B6",			Instruction::CPU_3DNOW},
		{"PFRSQIT1",		"mmreg,mm64",				"0F 0F /r A7",			Instruction::CPU_3DNOW},
		{"PFRSQRT",			"mmreg,mm64",				"0F 0F /r 97",			Instruction::CPU_3DNOW},
		{"PFSUB",			"mmreg,mm64",				"0F 0F /r 9A",			Instruction::CPU_3DNOW},
		{"PFSUBR",			"mmreg,mm64",				"0F 0F /r AA",			Instruction::CPU_3DNOW},
		{"PHADDD",			"mmreg,mm64",				"0F 38 02 /r",			Instruction::CPU_SSSE3},
		{"PHADDD",			"xmmreg,r/m128",			"66 0F 38 02 /r",		Instruction::CPU_SSSE3},
		{"PHADDSW",			"mmreg,mm64",				"0F 38 03 /r",			Instruction::CPU_SSSE3},
		{"PHADDSW",			"xmmreg,r/m128",			"66 0F 38 03 /r",		Instruction::CPU_SSSE3},
		{"PHADDW",			"mmreg,mm64",				"0F 38 01 /r",			Instruction::CPU_SSSE3},
		{"PHADDW",			"xmmreg,r/m128",			"66 0F 38 01 /r",		Instruction::CPU_SSSE3},
		{"PHMINPOSUW",		"xmmreg,r/m128",			"66 0F 38 41 /r",		Instruction::CPU_SSE4_1},
		{"PHSUBD",			"mmreg,mm64",				"0F 38 06 /r",			Instruction::CPU_SSSE3},
		{"PHSUBD",			"xmmreg,r/m128",			"66 0F 38 06 /r",		Instruction::CPU_SSSE3},
		{"PHSUBSW",			"mmreg,mm64",				"0F 38 07 /r",			Instruction::CPU_SSSE3},
		{"PHSUBSW",			"xmmreg,r/m128",			"66 0F 38 07 /r",		Instruction::CPU_SSSE3},
		{"PHSUBW",			"mmreg,mm64",				"0F 38 05 /r",			Instruction::CPU_SSSE3},
		{"PHSUBW",			"xmmreg,r/m128",			"66 0F 38 05 /r",		Instruction::CPU_SSSE3},
		{"PI2FD",			"mmreg,mm64",				"0F 0F /r 0D",			Instruction::CPU_3DNOW},
		{"PI2FW",			"mmreg,mm64",				"0F 0F /r 0C",			Instruction::CPU_ATHLON},
		{"PINSRB",			"xmmreg,reg32,imm8",		"66 0F 3A 20 /r ib",	Instruction::CPU_SSE4_1},
		{"PINSRB",			"xmmreg,mem8,imm8",			"66 0F 3A 20 /r ib",	Instruction::CPU_SSE4_1},
		{"PINSRD",			"xmmreg,r/m32,imm8",		"66 0F 3A 22 /r ib",	Instruction::CPU_SSE4_1},
		{"PINSRQ",			"xmmreg,r/m64,imm8",		"66 0F 3A 22 /r ib",	Instruction::CPU_SSE4_1 | Instruction::CPU_X64},
		{"PINSRW",			"mmreg,r/m16,imm8",			"0F C4 /r ib",			Instruction::CPU_KATMAI},
		{"PINSRW",			"xmmreg,r/m16,imm8",		"66 0F C4 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMACHRIW",		"mmreg,mem64",				"0F 5E /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMADDUBSW",		"mmreg,mm64",				"0F 38 04 /r",			Instruction::CPU_SSSE3},
		{"PMADDUBSW",		"xmmreg,r/m128",			"66 0F 38 04 /r",		Instruction::CPU_SSSE3},
		{"PMADDWD",			"mmreg,mm64",				"0F F5 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PMADDWD",			"xmmreg,r/m128",			"66 0F F5 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMAGW",			"mmreg,mm64",				"0F 52 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMAXSB",			"xmmreg,r/m128",			"66 0F 38 3C /r",		Instruction::CPU_SSE4_1},
		{"PMAXSD",			"xmmreg,r/m128",			"66 0F 38 3D /r",		Instruction::CPU_SSE4_1},
		{"PMAXSW",			"xmmreg,r/m128",			"66 0F EE /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMAXSW",			"mmreg,mm64",				"0F EE /r",				Instruction::CPU_KATMAI},
		{"PMAXUB",			"mmreg,mm64",				"0F DE /r",				Instruction::CPU_KATMAI},
		{"PMAXUB",			"xmmreg,r/m128",			"66 0F DE /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMINSB",			"xmmreg,r/m128",			"66 0F 38 38 /r",		Instruction::CPU_SSE4_1},
		{"PMINSD",			"xmmreg,r/m128",			"66 0F 38 39 /r",		Instruction::CPU_SSE4_1},
		{"PMINSW",			"mmreg,mm64",				"0F EA /r",				Instruction::CPU_KATMAI},
		{"PMINSW",			"xmmreg,r/m128",			"66 0F EA /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMINUB",			"mmreg,mm64",				"0F DA /r",				Instruction::CPU_KATMAI},
		{"PMINUB",			"xmmreg,r/m128",			"66 0F DA /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMINUD",			"xmmreg,r/m128",			"66 0F 38 3B /r",		Instruction::CPU_SSE4_1},
		{"PMOVMSKB",		"reg32,mmreg",				"0F D7 /r",				Instruction::CPU_KATMAI},
		{"PMOVMSKB",		"reg32,xmmreg",				"66 0F D7 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMOVSXBD",		"xmmreg,xmmreg",			"66 0F 38 21 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXBD",		"xmmreg,mem32",				"66 0F 38 21 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXBQ",		"xmmreg,xmmreg",			"66 0F 38 22 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXBQ",		"xmmreg,mem16",				"66 0F 38 22 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXBW",		"xmmreg,xmmreg",			"66 0F 38 20 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXBW",		"xmmreg,mem64",				"66 0F 38 20 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXDQ",		"xmmreg,xmmreg",			"66 0F 38 25 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXDQ",		"xmmreg,mem64",				"66 0F 38 25 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXWD",		"xmmreg,xmmreg",			"66 0F 38 23 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXWD",		"xmmreg,mem64",				"66 0F 38 23 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXWQ",		"xmmreg,xmmreg",			"66 0F 38 24 /r",		Instruction::CPU_SSE4_1},
		{"PMOVSXWQ",		"xmmreg,mem32",				"66 0F 38 24 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXBD",		"xmmreg,xmmreg",			"66 0F 38 31 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXBD",		"xmmreg,mem32",				"66 0F 38 31 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXBQ",		"xmmreg,xmmreg",			"66 0F 38 32 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXBQ",		"xmmreg,mem16",				"66 0F 38 32 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXBW",		"xmmreg,xmmreg",			"66 0F 38 30 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXBW",		"xmmreg,mem64",				"66 0F 38 30 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXDQ",		"xmmreg,xmmreg",			"66 0F 38 35 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXDQ",		"xmmreg,mem64",				"66 0F 38 35 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXWD",		"xmmreg,xmmreg",			"66 0F 38 33 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXWD",		"xmmreg,mem64",				"66 0F 38 33 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXWQ",		"xmmreg,xmmreg",			"66 0F 38 34 /r",		Instruction::CPU_SSE4_1},
		{"PMOVZXWQ",		"xmmreg,mem32",				"66 0F 38 34 /r",		Instruction::CPU_SSE4_1},
		{"PMULDQ",			"xmmreg,r/m128",			"66 0F 38 28 /r",		Instruction::CPU_SSE4_1},
		{"PMULHRIW",		"mmreg,mm64",				"0F 5D /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMULHRSW",		"mmreg,mm64",				"0F 38 0B /r",			Instruction::CPU_SSSE3 },
		{"PMULHRSW",		"xmmreg,r/m128",			"66 0F 38 0B /r",		Instruction::CPU_SSSE3 },
		{"PMULHRWA",		"mmreg,mm64",				"0F 0F /r B7",			Instruction::CPU_3DNOW},
		{"PMULHRWC",		"mmreg,mm64",				"0F 59 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMULHUW",			"mmreg,mm64",				"0F E4 /r",				Instruction::CPU_KATMAI},
		{"PMULHUW",			"xmmreg,r/m128",			"66 0F E4 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMULHW",			"mmreg,mm64",				"0F E5 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PMULHW",			"xmmreg,r/m128",			"66 0F E5 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMULLD",			"xmmreg,r/m128",			"66 0F 38 40 /r",		Instruction::CPU_SSE4_1},
		{"PMULLW",			"mmreg,mm64",				"0F D5 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PMULLW",			"xmmreg,r/m128",			"66 0F D5 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMULUDQ",			"mmreg,mm64",				"0F F4 /r",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMULUDQ",			"xmmreg,r/m128",			"66 0F F4 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PMVGEZB",			"mmreg,mem64",				"0F 5C /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMVLZB",			"mmreg,mem64",				"0F 5B /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMVNZB",			"mmreg,mem64",				"0F 5A /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PMVZB",			"mmreg,mem64",				"0F 58 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"POP",				"reg16",					"po 58 +r",				Instruction::CPU_8086},
		{"POP",				"reg32",					"po 58 +r",				Instruction::CPU_386},
		{"POP",				"reg64",					"po 58 +r",				Instruction::CPU_X64},
		{"POP",				"WORD r/m16",				"po 8F /0",				Instruction::CPU_8086},
		{"POP",				"DWORD r/m32",				"po 8F /0",				Instruction::CPU_386},
		{"POP",				"QWORD r/m64",				"po 8F /0",				Instruction::CPU_X64},
	//	{"POP",				"CS",						"0F",					Instruction::CPU_8086 | Instruction::CPU_UNDOC | Instruction::CPU_INVALID64},
	//	{"POP",				"DS",						"1F",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"POP",				"ES",						"07",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"POP",				"SS",						"17",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"POP",				"FS",						"0F A1",				Instruction::CPU_386},
	//	{"POP",				"GS",						"0F A9",				Instruction::CPU_386},
		{"POPA",			"",							"61",					Instruction::CPU_186 | Instruction::CPU_INVALID64},
		{"POPAD",			"",							"po 61",				Instruction::CPU_386 | Instruction::CPU_INVALID64},
		{"POPAW",			"",							"po 61",				Instruction::CPU_186 | Instruction::CPU_INVALID64},
		{"POPCNT",			"reg16,r/m16",				"F3 0F B8 /r",			Instruction::CPU_SSE4_2},
		{"POPCNT",			"reg32,r/m32",				"F3 0F B8 /r",			Instruction::CPU_SSE4_2},
		{"POPCNT",			"reg64,r/m64",				"F3 0F B8 /r",			Instruction::CPU_SSE4_2 | Instruction::CPU_X64},
		{"POPF",			"",							"9D",					Instruction::CPU_186},
		{"POPFD",			"",							"po 9D",				Instruction::CPU_386},
		{"POPFQ",			"",							"po 9D",				Instruction::CPU_X64},
		{"POPFW",			"",							"po 9D",				Instruction::CPU_186},
		{"POR",				"mmreg,mm64",				"0F EB /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"POR",				"xmmreg,r/m128",			"66 0F EB /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PREFETCH",		"mem",						"0F 0D /0",				Instruction::CPU_3DNOW},
		{"PREFETCHNTA",		"mem",						"0F 18 /0",				Instruction::CPU_KATMAI},
		{"PREFETCHT0",		"mem",						"0F 18 /1",				Instruction::CPU_KATMAI},
		{"PREFETCHT1",		"mem",						"0F 18 /2",				Instruction::CPU_KATMAI},
		{"PREFETCHT2",		"mem",						"0F 18 /3",				Instruction::CPU_KATMAI},
		{"PREFETCHW",		"mem",						"0F 0D /1",				Instruction::CPU_3DNOW},
		{"PSADBW",			"mmreg,mm64",				"0F F6 /r",				Instruction::CPU_KATMAI},
		{"PSADBW",			"xmmreg,r/m128",			"66 0F F6 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSHUFB",			"mmreg,mm64",				"0F 38 00 /r",			Instruction::CPU_SSSE3},
		{"PSHUFB",			"xmmreg,r/m128",			"66 0F 38 00 /r",		Instruction::CPU_SSSE3},
		{"PSHUFD",			"xmmreg,r/m128,imm8",		"66 0F 70 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSHUFHW",			"xmmreg,r/m128,imm8",		"p3 0F 70 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSHUFLW",			"xmmreg,r/m128,imm8",		"p2 0F 70 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSHUFW",			"mmreg,mm64,imm8",			"0F 70 /r ib",			Instruction::CPU_KATMAI},
		{"PSIGNB",			"mmreg,mm64",				"0F 38 08 /r",			Instruction::CPU_SSSE3},
		{"PSIGNB",			"xmmreg,r/m128",			"66 0f 38 08 /r",		Instruction::CPU_SSSE3},
		{"PSIGND",			"mmreg,mm64",				"0F 38 0a /r",			Instruction::CPU_SSSE3},
		{"PSIGND",			"xmmreg,r/m128",			"66 0f 38 0a /r",		Instruction::CPU_SSSE3},
		{"PSIGNW",			"mmreg,mm64",				"0F 38 09 /r",			Instruction::CPU_SSSE3},
		{"PSIGNW",			"xmmreg,r/m128",			"66 0f 38 09 /r",		Instruction::CPU_SSSE3},
		{"PSLLD",			"mmreg,mm64",				"0F F2 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSLLD",			"mmreg,imm8",				"0F 72 /6 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSLLD",			"xmmreg,r/m128",			"66 0F F2 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSLLD",			"xmmreg,imm8",				"66 0F 72 /6 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSLLQ",			"mmreg,mm64",				"0F F3 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSLLQ",			"mmreg,imm8",				"0F 73 /6 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSLLQ",			"xmmreg,r/m128",			"66 0F F3 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSLLQ",			"xmmreg,imm8",				"66 0F 73 /6 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSLLW",			"mmreg,mm64",				"0F F1 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSLLW",			"mmreg,imm8",				"0F 71 /6 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSLLW",			"xmmreg,r/m128",			"66 0F F1 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSLLW",			"xmmreg,imm8",				"66 0F 71 /6 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRAD",			"mmreg,mm64",				"0F E2 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRAD",			"mmreg,imm8",				"0F 72 /4 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRAD",			"xmmreg,r/m128",			"66 0F E2 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRAD",			"xmmreg,imm8",				"66 0F 72 /4 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRAW",			"mmreg,mm64",				"0F E1 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRAW",			"mmreg,imm8",				"0F 71 /4 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRAW",			"xmmreg,r/m128",			"66 0F E1 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRAW",			"xmmreg,imm8",				"66 0F 71 /4 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLD",			"mmreg,mm64",				"0F D2 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRLD",			"mmreg,imm8",				"0F 72 /2 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRLD",			"xmmreg,r/m128",			"66 0F D2 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLD",			"xmmreg,imm8",				"66 0F 72 /2 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLDQ",			"xmmreg,imm8",				"66 0F 73 /3 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLQ",			"mmreg,mm64",				"0F D3 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRLQ",			"mmreg,imm8",				"0F 73 /2 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRLQ",			"xmmreg,r/m128",			"66 0F D3 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLQ",			"xmmreg,imm8",				"66 0F 73 /2 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLW",			"mmreg,mm64",				"0F D1 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRLW",			"mmreg,imm8",				"0F 71 /2 ib",			Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSRLW",			"xmmreg,r/m128",			"66 0F D1 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSRLW",			"xmmreg,imm8",				"66 0F 71 /2 ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBB",			"mmreg,mm64",				"0F F8 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBB",			"xmmreg,r/m128",			"66 0F F8 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBD",			"mmreg,mm64",				"0F FA /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBD",			"xmmreg,r/m128",			"66 0F FA /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBQ",			"mmreg,mm64",				"0F FB /r",				Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBQ",			"xmmreg,r/m128",			"66 0F FB /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBSB",			"mmreg,mm64",				"0F E8 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBSB",			"xmmreg,r/m128",			"66 0F E8 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBSIW",			"mmreg,mm64",				"0F 55 /r",				Instruction::CPU_CYRIX | Instruction::CPU_MMX},
		{"PSUBSW",			"mmreg,mm64",				"0F E9 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBSW",			"xmmreg,r/m128",			"66 0F E9 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBUSB",			"mmreg,mm64",				"0F D8 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBUSB",			"xmmreg,r/m128",			"66 0F D8 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBUSW",			"mmreg,mm64",				"0F D9 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBUSW",			"xmmreg,r/m128",			"66 0F D9 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSUBW",			"mmreg,mm64",				"0F F9 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PSUBW",			"xmmreg,r/m128",			"66 0F F9 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PSWAPD",			"mmreg,mm64",				"0F 0F /r BB",			Instruction::CPU_ATHLON},
		{"PTEST",			"xmmreg,r/m128",			"66 0F 38 17 /r",		Instruction::CPU_SSE4_1},
		{"PUNPCKHBW",		"mmreg,mm64",				"0F 68 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PUNPCKHBW",		"xmmreg,r/m128",			"66 0F 68 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKHDQ",		"mmreg,mm64",				"0F 6A /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PUNPCKHDQ",		"xmmreg,r/m128",			"66 0F 6A /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKHQDQ",		"xmmreg,r/m128",			"66 0F 6D /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKHWD",		"mmreg,mm64",				"0F 69 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PUNPCKHWD",		"xmmreg,r/m128",			"66 0F 69 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKLBW",		"mmreg,mm64",				"0F 60 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PUNPCKLBW",		"xmmreg,r/m128",			"66 0F 60 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKLDQ",		"mmreg,mm64",				"0F 62 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PUNPCKLDQ",		"xmmreg,r/m128",			"66 0F 62 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKLQDQ",		"xmmreg,r/m128",			"66 0F 6C /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUNPCKLWD",		"mmreg,mm64",				"0F 61 /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PUNPCKLWD",		"xmmreg,r/m128",			"66 0F 61 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"PUSH",			"reg16",					"po 50 +r",				Instruction::CPU_8086},
		{"PUSH",			"reg32",					"po 50 +r",				Instruction::CPU_386},
		{"PUSH",			"reg64",					"po 50 +r",				Instruction::CPU_X64},
		{"PUSH",			"WORD r/m16",				"po FF /6",				Instruction::CPU_8086},
		{"PUSH",			"DWORD r/m32",				"po FF /6",				Instruction::CPU_386},
		{"PUSH",			"QWORD r/m64",				"po FF /6",				Instruction::CPU_X64},
	//	{"PUSH",			"CS",						"0E",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"PUSH",			"DS",						"1E",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"PUSH",			"ES",						"06",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"PUSH",			"SS",						"16",					Instruction::CPU_8086 | Instruction::CPU_INVALID64},
	//	{"PUSH",			"FS",						"0F A0",				Instruction::CPU_386},
	//	{"PUSH",			"GS",						"0F A8",				Instruction::CPU_386},
		{"PUSH",			"BYTE imm8",				"6A ib",				Instruction::CPU_286},
		{"PUSH",			"WORD imm16",				"po 68 iw",				Instruction::CPU_286},
		{"PUSH",			"DWORD imm32",				"po 68 id",				Instruction::CPU_386},
		{"PUSH",			"QWORD imm32",				"po 68 id",				Instruction::CPU_X64},
		{"PUSHA",			"",							"60",					Instruction::CPU_186 | Instruction::CPU_INVALID64},
		{"PUSHAD",			"",							"po 60",				Instruction::CPU_386 | Instruction::CPU_INVALID64},
		{"PUSHAW",			"",							"po 60",				Instruction::CPU_186 | Instruction::CPU_INVALID64},
		{"PUSHF",			"",							"9C",					Instruction::CPU_186},
		{"PUSHFD",			"",							"po 9C",				Instruction::CPU_386},
		{"PUSHFW",			"",							"po 9C",				Instruction::CPU_186},
		{"PXOR",			"mmreg,mm64",				"0F EF /r",				Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
		{"PXOR",			"xmmreg,r/m128",			"66 0F EF /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"RCL",				"BYTE r/m8,1",				"D0 /2",				Instruction::CPU_8086},
		{"RCL",				"BYTE r/m8,CL",				"D2 /2",				Instruction::CPU_8086},
		{"RCL",				"BYTE r/m8,imm8",			"C0 /2 ib",				Instruction::CPU_286},
		{"RCL",				"WORD r/m16,1",				"po D1 /2",				Instruction::CPU_8086},
		{"RCL",				"WORD r/m16,CL",			"po D3 /2",				Instruction::CPU_8086},
		{"RCL",				"WORD r/m16,imm8",			"po C1 /2 ib",			Instruction::CPU_286},
		{"RCL",				"DWORD r/m32,1",			"po D1 /2",				Instruction::CPU_386},
		{"RCL",				"DWORD r/m32,CL",			"po D3 /2",				Instruction::CPU_386},
		{"RCL",				"DWORD r/m32,imm8",			"po C1 /2 ib",			Instruction::CPU_386},
		{"RCL",				"DWORD r/m32,1",			"po D1 /2",				Instruction::CPU_X64},
		{"RCL",				"QWORD r/m64,CL",			"po D3 /2",				Instruction::CPU_X64},
		{"RCL",				"QWORD r/m64,imm8",			"po C1 /2 ib",			Instruction::CPU_X64},
		{"RCPPS",			"xmmreg,r/m128",			"0F 53 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"RCPSS",			"xmmreg,xmm32",				"p3 0F 53 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"RCR",				"BYTE r/m8,1",				"D0 /3",				Instruction::CPU_8086},
		{"RCR",				"BYTE r/m8,CL",				"D2 /3",				Instruction::CPU_8086},
		{"RCR",				"BYTE r/m8,imm8",			"C0 /3 ib",				Instruction::CPU_286},
		{"RCR",				"WORD r/m16,1",				"po D1 /3",				Instruction::CPU_8086},
		{"RCR",				"WORD r/m16,CL",			"po D3 /3",				Instruction::CPU_8086},
		{"RCR",				"WORD r/m16,imm8",			"po C1 /3 ib",			Instruction::CPU_286},
		{"RCR",				"DWORD r/m32,1",			"po D1 /3",				Instruction::CPU_386},
		{"RCR",				"DWORD r/m32,CL",			"po D3 /3",				Instruction::CPU_386},
		{"RCR",				"DWORD r/m32,imm8",			"po C1 /3 ib",			Instruction::CPU_386},
		{"RCR",				"QWORD r/m32,1",			"po D1 /3",				Instruction::CPU_X64},
		{"RCR",				"QWORD r/m32,CL",			"po D3 /3",				Instruction::CPU_X64},
		{"RCR",				"QWORD r/m32,imm8",			"po C1 /3 ib",			Instruction::CPU_X64},
		{"RDMSR",			"",							"0F 32",				Instruction::CPU_PENTIUM},
		{"RDPMC",			"",							"0F 33",				Instruction::CPU_P6},
	//	{"RDSHR",			"",							"0F 36",				Instruction::CPU_P6 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
		{"RDTSC",			"",							"0F 31",				Instruction::CPU_PENTIUM},
		{"REP INSB",		"",							"p3 6C",				Instruction::CPU_186},
		{"REP INSD",		"",							"p3 po 6D",				Instruction::CPU_386},
		{"REP INSW",		"",							"p3 po 6D",				Instruction::CPU_186},
		{"REP LODSB",		"",							"p3 AC",				Instruction::CPU_8086},
		{"REP LODSD",		"",							"p3 po AD",				Instruction::CPU_386},
		{"REP LODSW",		"",							"p3 po AD",				Instruction::CPU_8086},
		{"REP MOVSB",		"",							"p3 A4",				Instruction::CPU_8086},
		{"REP MOVSD",		"",							"p3 po A5",				Instruction::CPU_386},
		{"REP MOVSW",		"",							"p3 po A5",				Instruction::CPU_8086},
		{"REP OUTSB",		"",							"p3 6E",				Instruction::CPU_186},
		{"REP OUTSD",		"",							"p3 po 6F",				Instruction::CPU_386},
		{"REP OUTSW",		"",							"p3 po 6F",				Instruction::CPU_186},
		{"REP SCASB",		"",							"p3 AE",				Instruction::CPU_8086},
		{"REP SCASD",		"",							"p3 po AF",				Instruction::CPU_386},
		{"REP SCASW",		"",							"p3 po AF",				Instruction::CPU_8086},
		{"REP STOSB",		"",							"p3 AA",				Instruction::CPU_8086},
		{"REP STOSD",		"",							"p3 po AB",				Instruction::CPU_386},
		{"REP STOSW",		"",							"p3 po AB",				Instruction::CPU_8086},
		{"REPE CMPSB",		"",							"p3 A6",				Instruction::CPU_8086},
		{"REPE CMPSD",		"",							"p3 po A7",				Instruction::CPU_386},
		{"REPE CMPSW",		"",							"p3 po A7",				Instruction::CPU_8086},
		{"REPE SCASB",		"",							"p3 AE",				Instruction::CPU_8086},
		{"REPE SCASD",		"",							"p3 po AF",				Instruction::CPU_386},
		{"REPE SCASW",		"",							"p3 po AF",				Instruction::CPU_8086},
		{"REPNE CMPSB",		"",							"p2 A6",				Instruction::CPU_8086},
		{"REPNE CMPSD",		"",							"p2 po A7",				Instruction::CPU_386},
		{"REPNE CMPSW",		"",							"p2 po A7",				Instruction::CPU_8086},
		{"REPNE SCASB",		"",							"p2 AE",				Instruction::CPU_8086},
		{"REPNE SCASD",		"",							"p2 po AF",				Instruction::CPU_386},
		{"REPNE SCASW",		"",							"p2 po AF",				Instruction::CPU_8086},
		{"REPNZ CMPSB",		"",							"p2 A6",				Instruction::CPU_8086},
		{"REPNZ CMPSD",		"",							"p2 po A7",				Instruction::CPU_386},
		{"REPNZ CMPSW",		"",							"p2 po A7",				Instruction::CPU_8086},
		{"REPNZ SCASB",		"",							"p2 AE",				Instruction::CPU_8086},
		{"REPNZ SCASD",		"",							"p2 po AF",				Instruction::CPU_386},
		{"REPNZ SCASW",		"",							"p2 po AF",				Instruction::CPU_8086},
		{"REPZ CMPSB",		"",							"p3 A6",				Instruction::CPU_8086},
		{"REPZ CMPSD",		"",							"p3 po A7",				Instruction::CPU_386},
		{"REPZ CMPSW",		"",							"p3 po A7",				Instruction::CPU_8086},
		{"REPZ SCASB",		"",							"p3 AE",				Instruction::CPU_8086},
		{"REPZ SCASD",		"",							"p3 po AF",				Instruction::CPU_386},
		{"REPZ SCASW",		"",							"p3 po AF",				Instruction::CPU_8086},
		{"RET",				"",							"C3",					Instruction::CPU_8086},
		{"RET",				"imm16",					"C2 iw",				Instruction::CPU_8086},
	//	{"RETF",			"",							"CB",					Instruction::CPU_8086},
	//	{"RETF",			"imm16",					"CA iw",				Instruction::CPU_8086},
	//	{"RETN",			"",							"C3",					Instruction::CPU_8086},
	//	{"RETN",			"imm16",					"C2 iw",				Instruction::CPU_8086},
		{"ROL",				"BYTE r/m8,1",				"D0 /0",				Instruction::CPU_8086},
		{"ROL",				"BYTE r/m8,CL",				"D2 /0",				Instruction::CPU_8086},
		{"ROL",				"BYTE r/m8,imm8",			"C0 /0 ib",				Instruction::CPU_286},
		{"ROL",				"WORD r/m16,1",				"po D1 /0",				Instruction::CPU_8086},
		{"ROL",				"WORD r/m16,CL",			"po D3 /0",				Instruction::CPU_8086},
		{"ROL",				"WORD r/m16,imm8",			"po C1 /0 ib",			Instruction::CPU_286},
		{"ROL",				"DWORD r/m32,1",			"po D1 /0",				Instruction::CPU_386},
		{"ROL",				"DWORD r/m32,CL",			"po D3 /0",				Instruction::CPU_386},
		{"ROL",				"DWORD r/m32,imm8",			"po C1 /0 ib",			Instruction::CPU_386},
		{"ROL",				"QWORD r/m32,1",			"po D1 /0",				Instruction::CPU_X64},
		{"ROL",				"QWORD r/m32,CL",			"po D3 /0",				Instruction::CPU_X64},
		{"ROL",				"QWORD r/m32,imm8",			"po C1 /0 ib",			Instruction::CPU_X64},
		{"ROR",				"BYTE r/m8,1",				"D0 /1",				Instruction::CPU_8086},
		{"ROR",				"BYTE r/m8,CL",				"D2 /1",				Instruction::CPU_8086},
		{"ROR",				"BYTE r/m8,imm8",			"C0 /1 ib",				Instruction::CPU_286},
		{"ROR",				"WORD r/m16,1",				"po D1 /1",				Instruction::CPU_8086},
		{"ROR",				"WORD r/m16,CL",			"po D3 /1",				Instruction::CPU_8086},
		{"ROR",				"WORD r/m16,imm8",			"po C1 /1 ib",			Instruction::CPU_286},
		{"ROR",				"DWORD r/m32,1",			"po D1 /1",				Instruction::CPU_386},
		{"ROR",				"DWORD r/m32,CL",			"po D3 /1",				Instruction::CPU_386},
		{"ROR",				"DWORD r/m32,imm8",			"po C1 /1 ib",			Instruction::CPU_386},
		{"ROR",				"QWORD r/m64,1",			"po D1 /1",				Instruction::CPU_X64},
		{"ROR",				"QWORD r/m64,CL",			"po D3 /1",				Instruction::CPU_X64},
		{"ROR",				"QWORD r/m64,imm8",			"po C1 /1 ib",			Instruction::CPU_X64},
		{"ROUNDPD",			"xmmreg,r/m128,imm8",		"66 0F 3A 09 /r ib",	Instruction::CPU_SSE4_1},
		{"ROUNDPS",			"xmmreg,r/m128,imm8",		"66 0F 3A 08 /r ib",	Instruction::CPU_SSE4_1},
		{"ROUNDSD",			"xmmreg,r/m128,imm8",		"66 0F 3A 0B /r ib",	Instruction::CPU_SSE4_1},
		{"ROUNDSS",			"xmmreg,r/m128,imm8",		"66 0F 3A 0A /r ib",	Instruction::CPU_SSE4_1},
	//	{"RSDC",			"segreg,mem80",				"0F 79 /r",				Instruction::CPU_486 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
	//	{"RSLDT",			"mem80",					"0F 7B /0",				Instruction::CPU_486 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
		{"RSM",				"",							"0F AA",				Instruction::CPU_PENTIUM},
		{"RSQRTPS",			"xmmreg,r/m128",			"0F 52 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"RSQRTSS",			"xmmreg,xmm32",				"p3 0F 52 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
	//	{"RSTS",			"mem80",					"0F 7D /0",				Instruction::CPU_486 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
		{"SAHF",			"",							"9E",					Instruction::CPU_8086},
		{"SAL",				"BYTE r/m8,1",				"D0 /4",				Instruction::CPU_8086},
		{"SAL",				"BYTE r/m8,CL",				"D2 /4",				Instruction::CPU_8086},
		{"SAL",				"BYTE r/m8,imm8",			"C0 /4 ib",				Instruction::CPU_286},
		{"SAL",				"WORD r/m16,1",				"po D1 /4",				Instruction::CPU_8086},
		{"SAL",				"WORD r/m16,CL",			"po D3 /4",				Instruction::CPU_8086},
		{"SAL",				"WORD r/m16,imm8",			"po C1 /4 ib",			Instruction::CPU_286},
		{"SAL",				"DWORD r/m32,1",			"po D1 /4",				Instruction::CPU_386},
		{"SAL",				"DWORD r/m32,CL",			"po D3 /4",				Instruction::CPU_386},
		{"SAL",				"DWORD r/m32,imm8",			"po C1 /4 ib",			Instruction::CPU_386},
		{"SAL",				"QWORD r/m64,1",			"po D1 /4",				Instruction::CPU_X64},
		{"SAL",				"QWORD r/m64,CL",			"po D3 /4",				Instruction::CPU_X64},
		{"SAL",				"QWORD r/m64,imm8",			"po C1 /4 ib",			Instruction::CPU_X64},
		{"SAR",				"BYTE r/m8,1",				"D0 /7",				Instruction::CPU_8086},
		{"SAR",				"BYTE r/m8,CL",				"D2 /7",				Instruction::CPU_8086},
		{"SAR",				"BYTE r/m8,imm8",			"C0 /7 ib",				Instruction::CPU_286},
		{"SAR",				"WORD r/m16,1",				"po D1 /7",				Instruction::CPU_8086},
		{"SAR",				"WORD r/m16,CL",			"po D3 /7",				Instruction::CPU_8086},
		{"SAR",				"WORD r/m16,imm8",			"po C1 /7 ib",			Instruction::CPU_286},
		{"SAR",				"DWORD r/m32,1",			"po D1 /7",				Instruction::CPU_386},
		{"SAR",				"DWORD r/m32,CL",			"po D3 /7",				Instruction::CPU_386},
		{"SAR",				"DWORD r/m32,imm8",			"po C1 /7 ib",			Instruction::CPU_386},
		{"SAR",				"QWORD r/m64,1",			"po D1 /7",				Instruction::CPU_X64},
		{"SAR",				"QWORD r/m64,CL",			"po D3 /7",				Instruction::CPU_X64},
		{"SAR",				"QWORD r/m64,imm8",			"po C1 /7 ib",			Instruction::CPU_X64},
	//	{"SALC",			"",							"D6",					Instruction::CPU_8086 | Instruction::CPU_UNDOC | Instruction::CPU_INVALID64},
		{"SBB",				"r/m8,reg8",				"18 /r",				Instruction::CPU_8086},
		{"SBB",				"r/m16,reg16",				"po 19 /r",				Instruction::CPU_8086},
		{"SBB",				"r/m32,reg32",				"po 19 /r",				Instruction::CPU_386},
		{"SBB",				"r/m64,reg64",				"po 19 /r",				Instruction::CPU_X64},
		{"SBB",				"reg8,r/m8",				"1A /r",				Instruction::CPU_8086},
		{"SBB",				"reg16,r/m16",				"po 1B /r",				Instruction::CPU_8086},
		{"SBB",				"reg32,r/m32",				"po 1B /r",				Instruction::CPU_386},
		{"SBB",				"reg64,r/m64",				"po 1B /r",				Instruction::CPU_X64},
		{"SBB",				"BYTE r/m8,imm8",			"80 /3 ib",				Instruction::CPU_8086},
		{"SBB",				"WORD r/m16,imm16",			"po 81 /3 iw",			Instruction::CPU_8086},
		{"SBB",				"DWORD r/m32,imm32",		"po 81 /3 id",			Instruction::CPU_386},
		{"SBB",				"QWORD r/m64,imm32",		"po 81 /3 id",			Instruction::CPU_X64},
		{"SBB",				"WORD r/m16,imm8",			"po 83 /3 ib",			Instruction::CPU_8086},
		{"SBB",				"DWORD r/m32,imm8",			"po 83 /3 ib",			Instruction::CPU_386},
		{"SBB",				"QWORD r/m64,imm8",			"po 83 /3 ib",			Instruction::CPU_X64},
		{"SBB",				"AL,imm8",					"1C ib",				Instruction::CPU_8086},
		{"SBB",				"AX,imm16",					"po 1D iw",				Instruction::CPU_8086},
		{"SBB",				"EAX,imm32",				"po 1D id",				Instruction::CPU_386},
		{"SBB",				"RAX,imm32",				"po 1D id",				Instruction::CPU_X64},
		{"SCASB",			"",							"AE",					Instruction::CPU_8086},
		{"SCASD",			"",							"po AF",				Instruction::CPU_386},
		{"SCASQ",			"",							"po AF",				Instruction::CPU_X64},
		{"SCASW",			"",							"po AF",				Instruction::CPU_8086},
		{"SETA",			"r/m8",						"0F 97 /2",				Instruction::CPU_386},
		{"SETAE",			"r/m8",						"0F 93 /2",				Instruction::CPU_386},
		{"SETB",			"r/m8",						"0F 92 /2",				Instruction::CPU_386},
		{"SETBE",			"r/m8",						"0F 96 /2",				Instruction::CPU_386},
		{"SETC",			"r/m8",						"0F 92 /2",				Instruction::CPU_386},
		{"SETE",			"r/m8",						"0F 94 /2",				Instruction::CPU_386},
		{"SETG",			"r/m8",						"0F 9F /2",				Instruction::CPU_386},
		{"SETGE",			"r/m8",						"0F 9D /2",				Instruction::CPU_386},
		{"SETL",			"r/m8",						"0F 9C /2",				Instruction::CPU_386},
		{"SETLE",			"r/m8",						"0F 9E /2",				Instruction::CPU_386},
		{"SETNA",			"r/m8",						"0F 96 /2",				Instruction::CPU_386},
		{"SETNB",			"r/m8",						"0F 93 /2",				Instruction::CPU_386},
		{"SETNBE",			"r/m8",						"0F 97 /2",				Instruction::CPU_386},
		{"SETNC",			"r/m8",						"0F 93 /2",				Instruction::CPU_386},
		{"SETNE",			"r/m8",						"0F 95 /2",				Instruction::CPU_386},
		{"SETNEA",			"r/m8",						"0F 92 /2",				Instruction::CPU_386},
		{"SETNG",			"r/m8",						"0F 9E /2",				Instruction::CPU_386},
		{"SETNGE",			"r/m8",						"0F 9C /2",				Instruction::CPU_386},
		{"SETNL",			"r/m8",						"0F 9D /2",				Instruction::CPU_386},
		{"SETNLE",			"r/m8",						"0F 9F /2",				Instruction::CPU_386},
		{"SETNO",			"r/m8",						"0F 91 /2",				Instruction::CPU_386},
		{"SETNP",			"r/m8",						"0F 9B /2",				Instruction::CPU_386},
		{"SETNS",			"r/m8",						"0F 99 /2",				Instruction::CPU_386},
		{"SETNZ",			"r/m8",						"0F 95 /2",				Instruction::CPU_386},
		{"SETO",			"r/m8",						"0F 90 /2",				Instruction::CPU_386},
		{"SETP",			"r/m8",						"0F 9A /2",				Instruction::CPU_386},
		{"SETPE",			"r/m8",						"0F 9A /2",				Instruction::CPU_386},
		{"SETPO",			"r/m8",						"0F 9B /2",				Instruction::CPU_386},
		{"SETS",			"r/m8",						"0F 98 /2",				Instruction::CPU_386},
		{"SETZ",			"r/m8",						"0F 94 /2",				Instruction::CPU_386},
		{"SFENCE",			"",							"0F AE F8",				Instruction::CPU_KATMAI},
	//	{"SGDT",			"mem",						"0F 01 /0",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"SIDT",			"mem",						"0F 01 /1",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"SLDT",			"r/m16",					"0F 00 /0",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"SHL",				"BYTE r/m8,1",				"D0 /4",				Instruction::CPU_8086},
		{"SHL",				"BYTE r/m8,CL",				"D2 /4",				Instruction::CPU_8086},
		{"SHL",				"BYTE r/m8,imm8",			"C0 /4 ib",				Instruction::CPU_286},
		{"SHL",				"WORD r/m16,1",				"po D1 /4",				Instruction::CPU_8086},
		{"SHL",				"WORD r/m16,CL",			"po D3 /4",				Instruction::CPU_8086},
		{"SHL",				"WORD r/m16,imm8",			"po C1 /4 ib",			Instruction::CPU_286},
		{"SHL",				"DWORD r/m32,1",			"po D1 /4",				Instruction::CPU_386},
		{"SHL",				"DWORD r/m32,CL",			"po D3 /4",				Instruction::CPU_386},
		{"SHL",				"DWORD r/m32,imm8",			"po C1 /4 ib",			Instruction::CPU_386},
		{"SHL",				"QWORD r/m64,1",			"po D1 /4",				Instruction::CPU_X64},
		{"SHL",				"QWORD r/m64,CL",			"po D3 /4",				Instruction::CPU_X64},
		{"SHL",				"QWORD r/m64,imm8",			"po C1 /4 ib",			Instruction::CPU_X64},
		{"SHLD",			"r/m16,reg16,imm8",			"po 0F A4 /r ib",		Instruction::CPU_386},
		{"SHLD",			"r/m32,reg32,imm8",			"po 0F A4 /r ib",		Instruction::CPU_386},
		{"SHLD",			"r/m64,reg64,imm8",			"po 0F A4 /r ib",		Instruction::CPU_X64},
		{"SHLD",			"r/m16,reg16,CL",			"po 0F A5 /r",			Instruction::CPU_386},
		{"SHLD",			"r/m32,reg32,CL",			"po 0F A5 /r",			Instruction::CPU_386},
		{"SHLD",			"r/m64,reg64,CL",			"po 0F A5 /r",			Instruction::CPU_X64},
		{"SHR",				"BYTE r/m8,1",				"D0 /5",				Instruction::CPU_8086},
		{"SHR",				"BYTE r/m8,CL",				"D2 /5",				Instruction::CPU_8086},
		{"SHR",				"BYTE r/m8,imm8",			"C0 /5 ib",				Instruction::CPU_286},
		{"SHR",				"WORD r/m16,1",				"po D1 /5",				Instruction::CPU_8086},
		{"SHR",				"WORD r/m16,CL",			"po D3 /5",				Instruction::CPU_8086},
		{"SHR",				"WORD r/m16,imm8",			"po C1 /5 ib",			Instruction::CPU_286},
		{"SHR",				"DWORD r/m32,1",			"po D1 /5",				Instruction::CPU_386},
		{"SHR",				"DWORD r/m32,CL",			"po D3 /5",				Instruction::CPU_386},
		{"SHR",				"DWORD r/m32,imm8",			"po C1 /5 ib",			Instruction::CPU_386},
		{"SHR",				"QWORD r/m64,1",			"po D1 /5",				Instruction::CPU_X64},
		{"SHR",				"QWORD r/m64,CL",			"po D3 /5",				Instruction::CPU_X64},
		{"SHR",				"QWORD r/m64,imm8",			"po C1 /5 ib",			Instruction::CPU_X64},
		{"SHRD",			"r/m16,reg16,imm8",			"po 0F AC /r ib",		Instruction::CPU_386},
		{"SHRD",			"r/m32,reg32,imm8",			"po 0F AC /r ib",		Instruction::CPU_386},
		{"SHRD",			"r/m64,reg64,imm8",			"po 0F AC /r ib",		Instruction::CPU_X64},
		{"SHRD",			"r/m16,reg16,CL",			"po 0F AD /r",			Instruction::CPU_386},
		{"SHRD",			"r/m32,reg32,CL",			"po 0F AD /r",			Instruction::CPU_386},
		{"SHRD",			"r/m64,reg64,CL",			"po 0F AD /r",			Instruction::CPU_X64},
		{"SHUFPD",			"xmmreg,r/m128,imm8",		"66 0F C6 /r ib",		Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"SHUFPS",			"xmmreg,r/m128,imm8",		"0F C6 /r ib",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
	//	{"SMI",				"",							"F1",					Instruction::CPU_386 | Instruction::CPU_UNDOC},
		{"SMINT",			"",							"0F 38",				Instruction::CPU_P6 | Instruction::CPU_CYRIX},
		{"SMINTOLD",		"",							"0F 7E",				Instruction::CPU_486 | Instruction::CPU_CYRIX},
	//	{"SMSW",			"r/m16",					"0F 01 /4",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"SQRTPD",			"xmmreg,r/m128",			"66 0F 51 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"SQRTPS",			"xmmreg,r/m128",			"0F 51 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"SQRTSD",			"xmmreg,xmm64",				"p2 0F 51 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"SQRTSS",			"xmmreg,xmm32",				"p3 0F 51 /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"STC",				"",							"F9",					Instruction::CPU_8086},
		{"STD",				"",							"FD",					Instruction::CPU_8086},
		{"STI",				"",							"FB",					Instruction::CPU_8086},
		{"STMXCSR",			"mem32",					"0F AE /3",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"STOSB",			"",							"AA",					Instruction::CPU_8086},
		{"STOSD",			"",							"po AB",				Instruction::CPU_386},
		{"STOSQ",			"",							"po AB",				Instruction::CPU_X64},
		{"STOSW",			"",							"po AB",				Instruction::CPU_8086},
	//	{"STR",				"r/m16",					"0F 00 /1",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"SUB",				"r/m8,reg8",				"28 /r",				Instruction::CPU_8086},
		{"SUB",				"r/m16,reg16",				"po 29 /r",				Instruction::CPU_8086},
		{"SUB",				"r/m32,reg32",				"po 29 /r",				Instruction::CPU_386},
		{"SUB",				"r/m64,reg64",				"po 29 /r",				Instruction::CPU_X64},
		{"SUB",				"reg8,r/m8",				"2A /r",				Instruction::CPU_8086},
		{"SUB",				"reg16,r/m16",				"po 2B /r",				Instruction::CPU_8086},
		{"SUB",				"reg32,r/m32",				"po 2B /r",				Instruction::CPU_386},
		{"SUB",				"reg64,r/m64",				"po 2B /r",				Instruction::CPU_X64},
		{"SUB",				"BYTE r/m8,imm8",			"80 /5 ib",				Instruction::CPU_8086},
		{"SUB",				"WORD r/m16,imm16",			"po 81 /5 iw",			Instruction::CPU_8086},
		{"SUB",				"DWORD r/m32,imm32",		"po 81 /5 id",			Instruction::CPU_386},
		{"SUB",				"QWORD r/m64,imm32",		"po 81 /5 id",			Instruction::CPU_X64},
		{"SUB",				"WORD r/m16,imm8",			"po 83 /5 ib",			Instruction::CPU_8086},
		{"SUB",				"DWORD r/m32,imm8",			"po 83 /5 ib",			Instruction::CPU_386},
		{"SUB",				"QWORD r/m64,imm8",			"po 83 /5 ib",			Instruction::CPU_X64},
		{"SUB",				"AL,imm8",					"2C ib",				Instruction::CPU_8086},
		{"SUB",				"AX,imm16",					"po 2D iw",				Instruction::CPU_8086},
		{"SUB",				"EAX,imm32",				"po 2D id",				Instruction::CPU_386},
		{"SUB",				"RAX,imm32",				"po 2D id",				Instruction::CPU_X64},
		{"SUBPD",			"xmmreg,r/m128",			"66 0F 5C /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"SUBPS",			"xmmreg,r/m128",			"0F 5C /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"SUBSD",			"xmmreg,xmm64",				"p2 0F 5C /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"SUBSS",			"xmmreg,xmm32",				"p3 0F 5C /r",			Instruction::CPU_KATMAI | Instruction::CPU_SSE},
	//	{"SVDC",			"mem80,segreg",				"0F 78 /r",				Instruction::CPU_486 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
	//	{"SVLDT",			"mem80",					"0F 7A /0",				Instruction::CPU_486 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
	//	{"SVTS",			"mem80",					"0F 7C /0",				Instruction::CPU_486 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
	//	{"SYSCALL",			"",							"0F 05",				Instruction::CPU_P6 | Instruction::CPU_AMD},
		{"SYSENTER",		"",							"0F 34",				Instruction::CPU_P6 | Instruction::CPU_INVALID64},
	//	{"SYSEXIT",			"",							"0F 35",				Instruction::CPU_P6 | Instruction::CPU_PRIV | Instruction::CPU_INVALID64},
	//	{"SYSRET",			"",							"0F 07",				Instruction::CPU_P6 | Instruction::CPU_AMD | Instruction::CPU_PRIV},
		{"TEST",			"r/m8,reg8",				"84 /r",				Instruction::CPU_8086},
		{"TEST",			"r/m16,reg16",				"po 85 /r",				Instruction::CPU_8086},
		{"TEST",			"r/m32,reg32",				"po 85 /r",				Instruction::CPU_386},
		{"TEST",			"r/m64,reg64",				"po 85 /r",				Instruction::CPU_X64},
		{"TEST",			"BYTE r/m8,imm8",			"F6 /0 ib",				Instruction::CPU_8086},
		{"TEST",			"WORD r/m16,imm16",			"po F7 /0 iw",			Instruction::CPU_8086},
		{"TEST",			"DWORD r/m32,imm32",		"po F7 /0 id",			Instruction::CPU_386},
		{"TEST",			"QWORD r/m64,imm32",		"po F7 /0 id",			Instruction::CPU_X64},
		{"TEST",			"AL,imm8",					"A8 ib",				Instruction::CPU_8086},
		{"TEST",			"AX,imm16",					"po A9 iw",				Instruction::CPU_8086},
		{"TEST",			"EAX,imm32",				"po A9 id",				Instruction::CPU_386},
		{"TEST",			"RAX,imm32",				"po A9 id",				Instruction::CPU_X64},
		{"UCOMISD",			"xmmreg,xmm64",				"66 0F 2E /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"UCOMISS",			"xmmreg,xmm32",				"0F 2E /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"UD2",				"",							"0F 0B",				Instruction::CPU_286},
	//	{"UMOV",			"r/m8,reg8",				"0F 10 /r",				Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"UMOV",			"r/m16,reg16",				"po 0F 11 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"UMOV",			"r/m32,reg32",				"po 0F 11 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"UMOV",			"reg8,r/m8",				"0F 12 /r",				Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"UMOV",			"reg16,r/m16",				"po 0F 13 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"UMOV",			"reg32,r/m32",				"po 0F 13 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
		{"UNPCKHPD",		"xmmreg,r/m128",			"66 0F 15 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"UNPCKHPS",		"xmmreg,r/m128",			"0F 15 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
		{"UNPCKLPD",		"xmmreg,r/m128",			"66 0F 14 /r",			Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
		{"UNPCKLPS",		"xmmreg,r/m128",			"0F 14 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
	//	{"VERR",			"r/m16",					"0F 00 /4",				Instruction::CPU_286 | Instruction::CPU_PRIV},
	//	{"VERW",			"r/m16",					"0F 00 /5",				Instruction::CPU_286 | Instruction::CPU_PRIV},
		{"WAIT",			"",							"9B",					Instruction::CPU_8086},
	//	{"WBINVD",			"",							"0F 09",				Instruction::CPU_486},
		{"WRMSR",			"",							"0F 30",				Instruction::CPU_PENTIUM},
	//	{"WRSHR",			"",							"0F 37",				Instruction::CPU_P6 | Instruction::CPU_CYRIX | Instruction::CPU_SMM},
		{"XADD",			"r/m8,reg8",				"0F C0 /r",				Instruction::CPU_486},
		{"XADD",			"r/m16,reg16",				"po 0F C1 /r",			Instruction::CPU_486},
		{"XADD",			"r/m32,reg32",				"po 0F C1 /r",			Instruction::CPU_486},
		{"XADD",			"r/m64,reg64",				"po 0F C1 /r",			Instruction::CPU_X64},
	//	{"XBTS",			"reg16,r/m16",				"po 0F A6 /r",			Instruction::CPU_386 | Instruction::CPU_UNDOC},
	//	{"XBTS",			"reg32,r/m32",				"po 0F A6 /r",			Instruction::::CPU_386 | Instruction::CPU_UNDOC},
		{"XCHG",			"reg8,r/m8",				"86 /r",				Instruction::CPU_8086},
		{"XCHG",			"reg16,r/m16",				"po 87 /r",				Instruction::CPU_8086},
		{"XCHG",			"reg32,r/m32",				"po 87 /r",				Instruction::CPU_386},
		{"XCHG",			"reg64,r/m64",				"po 87 /r",				Instruction::CPU_X64},
		{"XCHG",			"r/m8,reg8",				"86 /r",				Instruction::CPU_8086},
		{"XCHG",			"r/m16,reg16",				"po 87 /r",				Instruction::CPU_8086},
		{"XCHG",			"r/m32,reg32",				"po 87 /r",				Instruction::CPU_386},
		{"XCHG",			"r/m64,reg64",				"po 87 /r",				Instruction::CPU_X64},
		{"XCHG",			"AX,reg16",					"po 90 +r",				Instruction::CPU_8086},
		{"XCHG",			"EAX,reg32",				"po 90 +r",				Instruction::CPU_386},
		{"XCHG",			"RAX,reg64",				"po 90 +r",				Instruction::CPU_X64},
		{"XCHG",			"reg16,AX",					"po 90 +r",				Instruction::CPU_8086},
		{"XCHG",			"reg32,EAX",				"po 90 +r",				Instruction::CPU_386},
		{"XCHG",			"reg64,RAX",				"po 90 +r",				Instruction::CPU_X64},
		{"XLATB",			"",							"D7",					Instruction::CPU_8086},
		{"XOR",				"r/m8,reg8",				"30 /r",				Instruction::CPU_8086},
		{"XOR",				"r/m16,reg16",				"po 31 /r",				Instruction::CPU_8086},
		{"XOR",				"r/m32,reg32",				"po 31 /r",				Instruction::CPU_386},
		{"XOR",				"r/m64,reg64",				"po 31 /r",				Instruction::CPU_X64},
		{"XOR",				"reg8,r/m8",				"32 /r",				Instruction::CPU_8086},
		{"XOR",				"reg16,r/m16",				"po 33 /r",				Instruction::CPU_8086},
		{"XOR",				"reg32,r/m32",				"po 33 /r",				Instruction::CPU_386},
		{"XOR",				"reg64,r/m64",				"po 33 /r",				Instruction::CPU_X64},
		{"XOR",				"BYTE r/m8,imm8",			"80 /6 ib",				Instruction::CPU_8086},
		{"XOR",				"WORD r/m16,imm16",			"po 81 /6 iw",			Instruction::CPU_8086},
		{"XOR",				"DWORD r/m32,imm32",		"po 81 /6 id",			Instruction::CPU_386},
		{"XOR",				"QWORD r/m64,imm32",		"po 81 /6 id",			Instruction::CPU_X64},
		{"XOR",				"WORD r/m16,imm8",			"po 83 /6 ib",			Instruction::CPU_8086},
		{"XOR",				"DWORD r/m32,imm8",			"po 83 /6 ib",			Instruction::CPU_386},
		{"XOR",				"QWORD r/m64,imm8",			"po 83 /6 ib",			Instruction::CPU_X64},
		{"XOR",				"AL,imm8",					"34 ib",				Instruction::CPU_8086},
		{"XOR",				"AX,imm16",					"po 35 iw",				Instruction::CPU_8086},
		{"XOR",				"EAX,imm32",				"po 35 id",				Instruction::CPU_386},
		{"XOR",				"RAX,imm32",				"po 35 id",				Instruction::CPU_X64},
		{"XORPS",			"xmmreg,r/m128",			"0F 57 /r",				Instruction::CPU_KATMAI | Instruction::CPU_SSE},
	};

	const int InstructionSet::numInstructions = sizeof(instructionSet) / sizeof(Instruction::Syntax);

	InstructionSet::InstructionSet()
	{
		intrinsicMap = new Instruction[numInstructions];

		for(int k = 0; k < numInstructions; k++)
		{
			intrinsicMap[k] = Instruction(&instructionSet[k]);
		}

		//generateIntrinsics();   // Uncomment this line when you make changes to the instruction set
	}

	InstructionSet::~InstructionSet()
	{
		delete[] intrinsicMap;
	}

	const Instruction *InstructionSet::instruction(int i)
	{
		return &intrinsicMap[i];
	}

	void InstructionSet::generateIntrinsics()
	{
		assert(intrinsicMap);

		// Check alphabetical order
		for(int k = 0; k < numInstructions; k++)
		{
			if(k != 0)
			{
				if(strcmp(instructionSet[k - 1].mnemonic, instructionSet[k].mnemonic) > 0)
				{
					assert(false);
				}
			}
		}

		FILE *intrinsics = fopen("Intrinsics.hpp", "w");

		fprintf(intrinsics, "/* Automatically generated file, do not modify */\n"
		                    "/* To regenerate this file uncomment generateIntrinsics() in InstructionSet.cpp */\n\n");

		fprintf(intrinsics, "#ifndef SOFTWIRE_NO_INTRINSICS\n\n");

		fprintf(intrinsics, "typedef OperandIMM IMM;\n");
		fprintf(intrinsics, "typedef OperandAL AL;\n");
		fprintf(intrinsics, "typedef OperandAX AX;\n");
		fprintf(intrinsics, "typedef OperandEAX EAX;\n");
		fprintf(intrinsics, "typedef OperandRAX RAX;\n");
		fprintf(intrinsics, "typedef OperandDX DX;\n");
		fprintf(intrinsics, "typedef OperandCL CL;\n");
		fprintf(intrinsics, "typedef OperandCX CX;\n");
		fprintf(intrinsics, "typedef OperandECX ECX;\n");
		fprintf(intrinsics, "typedef OperandST0 ST0;\n");
		fprintf(intrinsics, "typedef OperandREG8 REG8;\n");
		fprintf(intrinsics, "typedef OperandREG16 REG16;\n");
		fprintf(intrinsics, "typedef OperandREG32 REG32;\n");
		fprintf(intrinsics, "typedef OperandREG64 REG64;\n");
		fprintf(intrinsics, "typedef OperandFPUREG FPUREG;\n");
		fprintf(intrinsics, "typedef OperandMMREG MMREG;\n");
		fprintf(intrinsics, "typedef OperandXMMREG XMMREG;\n");
		fprintf(intrinsics, "typedef OperandMEM8 MEM8;\n");
		fprintf(intrinsics, "typedef OperandMEM16 MEM16;\n");
		fprintf(intrinsics, "typedef OperandMEM32 MEM32;\n");
		fprintf(intrinsics, "typedef OperandMEM64 MEM64;\n");
		fprintf(intrinsics, "typedef OperandMEM128 MEM128;\n");
		fprintf(intrinsics, "typedef OperandR_M8 R_M8;\n");
		fprintf(intrinsics, "typedef OperandR_M16 R_M16;\n");
		fprintf(intrinsics, "typedef OperandR_M32 R_M32;\n");
		fprintf(intrinsics, "typedef OperandR_M64 R_M64;\n");
		fprintf(intrinsics, "typedef OperandR_M128 R_M128;\n");
		fprintf(intrinsics, "typedef OperandXMM32 XMM32;\n");
		fprintf(intrinsics, "typedef OperandXMM64 XMM64;\n");
		fprintf(intrinsics, "typedef OperandMM64 MM64;\n");
		fprintf(intrinsics, "typedef OperandREF REF;\n");
		fprintf(intrinsics, "\n");
		fprintf(intrinsics, "typedef unsigned char byte;\n");
		fprintf(intrinsics, "typedef unsigned short word;\n");
		fprintf(intrinsics, "typedef unsigned int dword;\n");
		fprintf(intrinsics, "typedef unsigned __int64 qword;\n");
		fprintf(intrinsics, "\n");
		fprintf(intrinsics, "#define enc virtual Encoding*\n");
		fprintf(intrinsics, "\n");

		struct InstructionSignature
		{
			const char *mnemonic;

			const char *firstOperand;
			const char *secondOperand;
			const char *thirdOperand;

			Operand::Type firstType;
			Operand::Type secondType;
			Operand::Type thirdType;
		};

		InstructionSignature *uniqueSignature = new InstructionSignature[10000];
		int n = 0;	// Number of unique instructions

		for(int t = 0; t < numInstructions; t++)
		{
			const Instruction *instruction = &intrinsicMap[t];

			char mnemonic[256] = {0};
			strcpy(mnemonic, instruction->getMnemonic());
			_strlwr(mnemonic);
			if(mnemonic[3] == ' ') mnemonic[3] = '_';	// Append REP prefix
			if(mnemonic[4] == ' ') mnemonic[4] = '_';	// Append LOCK prefix
			if(mnemonic[5] == ' ') mnemonic[5] = '_';	// Append REPNE/REPNZ prefix

			Operand::Type t1 = instruction->getFirstOperand();
			Operand::Type t2 = instruction->getSecondOperand();
			Operand::Type t3 = instruction->getThirdOperand();

			const Operand::Register subtypeTable[] =
			{
				{Operand::OPERAND_VOID,		0},

				{Operand::OPERAND_REF,		"REF"},

				{Operand::OPERAND_IMM,		"dword"},
				{Operand::OPERAND_EXT8,		"byte"},
				{Operand::OPERAND_IMM8,		"byte"},
				{Operand::OPERAND_IMM16,	"word"},
				{Operand::OPERAND_IMM32,	"dword"},
			//	{Operand::OPERAND_IMM64,	"qword"},

				{Operand::OPERAND_REG8,		"REG8"},
				{Operand::OPERAND_REG16,	"REG16"},
				{Operand::OPERAND_REG32,	"REG32"},
				{Operand::OPERAND_REG64,	"REG64"},
				{Operand::OPERAND_FPUREG,	"FPUREG"},
				{Operand::OPERAND_MMREG,	"MMREG"},
				{Operand::OPERAND_XMMREG,	"XMMREG"},

				// Specializations that don't offer significant benefit
				// Placed lower to avoid outputting them
				{Operand::OPERAND_AL,		"AL"},
				{Operand::OPERAND_AX,		"AX"},
				{Operand::OPERAND_EAX,		"EAX"},
				{Operand::OPERAND_RAX,		"RAX"},
				{Operand::OPERAND_DX,		"DX"},
				{Operand::OPERAND_CL,		"CL"},
				{Operand::OPERAND_CX,		"CX"},
				{Operand::OPERAND_ECX,		"ECX"},
				{Operand::OPERAND_ST0,		"ST0"},

				{Operand::OPERAND_MEM8,		"MEM8"},
				{Operand::OPERAND_MEM16,	"MEM16"},
				{Operand::OPERAND_MEM32,	"MEM32"},
				{Operand::OPERAND_MEM64,	"MEM64"},
				{Operand::OPERAND_MEM128,	"MEM128"},

				{Operand::OPERAND_R_M8,		"R_M8"},
				{Operand::OPERAND_R_M16,	"R_M16"},
				{Operand::OPERAND_R_M32,	"R_M32"},
				{Operand::OPERAND_R_M64,	"R_M64"},
				{Operand::OPERAND_R_M128,	"R_M128"},

				{Operand::OPERAND_XMM32,	"XMM32"},
				{Operand::OPERAND_XMM64,	"XMM64"},
				{Operand::OPERAND_MM64,		"MM64"}
			};

			for(int i = 0; i < sizeof(subtypeTable) / sizeof(Operand::Register); i++)
			for(int j = 0; j < sizeof(subtypeTable) / sizeof(Operand::Register); j++)
			for(int k = 0; k < sizeof(subtypeTable) / sizeof(Operand::Register); k++)
			{
				if(Operand::isSubtypeOf(subtypeTable[i].type, t1))
				if(Operand::isSubtypeOf(subtypeTable[j].type, t2))
				if(Operand::isSubtypeOf(subtypeTable[k].type, t3))
				{
					int u = 0;

					for(u = 0; u < n; u++)
					{
						// Must have unique signature
						if(strcmp(instruction->getMnemonic(), uniqueSignature[u].mnemonic) == 0)
						if(strcmp(subtypeTable[i].notation, uniqueSignature[u].firstOperand) == 0)
						if(strcmp(subtypeTable[j].notation, uniqueSignature[u].secondOperand) == 0)
						if(strcmp(subtypeTable[k].notation, uniqueSignature[u].thirdOperand) == 0)
						{
							break;
						}

						// Don't output specialized instructions
						if(strcmp(instruction->getMnemonic(), uniqueSignature[u].mnemonic) == 0)
						if(Operand::isSubtypeOf(subtypeTable[i].type, uniqueSignature[u].firstType))
						if(Operand::isSubtypeOf(subtypeTable[j].type, uniqueSignature[u].secondType))
						if(Operand::isSubtypeOf(subtypeTable[k].type, uniqueSignature[u].thirdType))
						{
							break;
						}
					}

					if(u < n)
					{
						continue;
					}

					fprintf(intrinsics, "enc %s(", mnemonic);
					if(subtypeTable[i].notation) fprintf(intrinsics, "%s a", subtypeTable[i].notation);
					if(subtypeTable[j].notation) fprintf(intrinsics, ",%s b", subtypeTable[j].notation);
					if(subtypeTable[k].notation) fprintf(intrinsics, ",%s c", subtypeTable[k].notation);
					fprintf(intrinsics, "){return x86(%d", t);
					if(subtypeTable[i].notation)
					{
						fprintf(intrinsics, ",");
						if(Operand::isSubtypeOf(subtypeTable[i].type, Operand::OPERAND_IMM) &&
							subtypeTable[i].type != Operand::OPERAND_REF)
						{
							fprintf(intrinsics, "(IMM)");
						}
						fprintf(intrinsics, "a");
					}
					if(subtypeTable[j].notation)
					{
						fprintf(intrinsics, ",");
						if(Operand::isSubtypeOf(subtypeTable[j].type, Operand::OPERAND_IMM) &&
							subtypeTable[j].type != Operand::OPERAND_REF)
						{
							fprintf(intrinsics, "(IMM)");
						}
						fprintf(intrinsics, "b");
					}
					if(subtypeTable[k].notation)
					{
						fprintf(intrinsics, ",");
						if(Operand::isSubtypeOf(subtypeTable[k].type, Operand::OPERAND_IMM) &&
							subtypeTable[k].type != Operand::OPERAND_REF)
						{
							fprintf(intrinsics, "(IMM)");
						}
						fprintf(intrinsics, "c");
					}
					fprintf(intrinsics, ");}\n");

					printf("%s\n", mnemonic);

					uniqueSignature[n].mnemonic = instruction->getMnemonic();
					uniqueSignature[n].firstOperand = subtypeTable[i].notation;
					uniqueSignature[n].secondOperand = subtypeTable[j].notation;
					uniqueSignature[n].thirdOperand = subtypeTable[k].notation;
					uniqueSignature[n].firstType = subtypeTable[i].type;
					uniqueSignature[n].secondType = subtypeTable[j].type;
					uniqueSignature[n].thirdType = subtypeTable[k].type;
					n++;
				}
			}
		}

		fprintf(intrinsics, "\n");
		fprintf(intrinsics, "#undef enc\n\n");
		fprintf(intrinsics, "#endif   // SOFTWIRE_NO_INTRINSICS\n");

		delete[] uniqueSignature;
		fclose(intrinsics);
	}

	int InstructionSet::strcmp(const char *string1, const char *string2)
	{
		if(!string1 || !string2)
		{
			return (string1 == string2) ? 0 : -1;
		}

		return ::strcmp(string1, string2);
	}
}
